TL16C752D Datasheet, PDF (38/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
www.ti.com
8.5.15 FIFO Ready Register
The FIFO ready register provides realtime status of the transmit and receive FIFOs of both channels. Table 19
shows the FIFO ready register bit settings. The trigger level mentioned in Table 19 refers to the setting in either
FCR (when TLR value is 0), or TLR (when it has a nonzero value).
Table 19. FIFO Ready Register
BIT
BIT SETTINGS
0
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel A.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel A.
1
0 = There are fewer than a TX trigger level number of spaces available in the TX FIFO of channel B.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO of channel B.
3:2
Unused, always 0
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel A.
4
1 = The RX FIFO of channel A has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
0 = There are fewer than a RX trigger level number of characters in the RX FIFO of channel B.
5
1 = The RX FIFO of channel B has more than a RX trigger level number of characters available for reading or a timeout
condition has occurred.
7:6
Unused, always 0
The FIFORdy register is a read only register and can be accessed when any of the two UARTs are selected.
CSA or CSB = 0, MCR[2] (FIFORdy Enable) is a logic 1, and loopback is disabled. Its address is 111.
8.5.16 Alternate Function Register (AFR)
The AFR is used to enable some extra functionality beyond the capabilities of the original TL16C752B. The first
of these is a concurrent write mode, which can be useful in more expediently setting up all four UART channels.
The second addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to
115.2 bps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTRx)
per channel, which is timed to keep the RS-485 driver enabled as long as transmit data is pending.
The AFR is located at A[2:0] = 010 when LCR[7:5] = 100.
Table 20. AFR Bit Settings
BIT
BIT SETTINGS
0
CONC enables the concurrent write of all four (754) or two (752) channels simultaneously, which helps speed up
initialization. Ensure that any indirect addressing modes have been enabled before using.
1
IREN enables the IrDA SIR mode. This mode is only specified to 115.2 bps; TI does not recommend the use of this
mode at higher speeds.
485EN enables the half duplex RS-485 mode and causes the DTRx output to be set high whenever there is any data in
2
the THR or TSR and to be held high until the delay set by DLY2:0 has expired, at which time it is set low. The DTRx
output is intended to drive the enabled input of an RS-485 driver. When this bit is set, the transmitter interrupts are held
off until the TSR is empty, unless 485LG is set.
485LG is set when the 485EN is set. This bit indicates that a relatively large data block is being set, requiring more than
3
a single load of the xmt fifo. In this case, the transmitter interrupts occur as in the standard RS-232 mode, either when
the xmt fifo contents drop below the xmt threshold or when the xmt fifo is empty.
RCVEN is valid only when 485EN or IREN is set, and allows the serial receiver to listen in or snoop on the RS485 traffic
or IrDA traffic. RS485 mode is generally considered half duplex, and usually a node is either driving or receiving, but
there can be cases when it is advantageous to verify what you are sending. This can be used to detect collisions or as
part of an arbitration mechanism on the bus. When both RCVEN and 485EN are set, the receiver stores any data
presented on RX, if any. Note that implies that the external RS485 receiver is enabled. Whenever 485EN is cleared, the
serial receiver is enabled for normal full duplex RS232 traffic. If RCVEN is cleared while 485EN is set, the receiver is
disabled while that channel is transmitting. SIR is also considered half duplex. Often the light energy from the transmitting
4
LED is coupled back into the receiving PIN diode, which creates an input data stream that is not of interest to the host.
Disabling the receiver (clearing RCVEN) prevents this reception, and eliminates the task of unloading the data. On the
other hand, for diagnostic or other purposes, it may be useful to observe this data stream. For example, a mirror could be
used to intentionally couple the output LED to the input PIN. For these cases, RCVEN could be set to enable the
receiver.
NOTE: When RCVEN is cleared (set to 0), the character timeout interrupt is not available, even in RSA-232 mode. This
can be useful when checking code for valid threshold interrupts, as the timeout interrupt will not override the threshold
interrupt.
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