TL16C752D Datasheet, PDF (22/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
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8.3.1.8 Interrupts
The TL16C752D UART has interrupt generation and prioritization (six prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to
an interrupt generation. The IER also can disable the interrupt system by clearing bits 0 to 3, 5 to 7. When an
interrupt is generated, the interrupt identification register (IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5−0]. Table 4 summarizes the interrupt control functions.
IIR[5–0]
000001
000110
PRIORITY
LEVEL
None
1
001100
2
000100
2
000010
3
000000
4
010000
5
100000
6
Table 4. Interrupt Control Functions
INTERRUPT
TYPE
None
Receiver line
status
RX timeout
RHR interrupt
THR interrupt
Modem status
Xoff interrupt
CTS, RTS
INTERRUPT SOURCE
INTERRUPT RESET METHOD
None
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
Stale data in RX FIFO
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level (FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level (FIFO
enable)
MSR[3:0] = 0
Receive Xoff character or
characters/special character
RTS pin or CTS pin change state from
active (low) to inactive (high)
None
FE < PE < BI: All erroneous characters are
read from the RX FIFO. OE: Read LSR
Read RHR
Read RHR
Read IIR or a write to the THR
Read MSR
Receive Xon character or characters/Read of
IIR
Read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the RX
FIFO. Reading the RX FIFO updates LSR[4–2] to the appropriate status for the new character at the top of the
FIFO. If the RX FIFO is empty, then LSR[4–2] is all 0.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of
the ISR.
8.3.1.9 Interrupt Mode Operation
In interrupt mode (if any bit of IER[3:0] is 1), the processor is informed of the status of the receiver and
transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register
(LSR) to see if any interrupt needs to be serviced. Figure 20 shows interrupt mode operation.
Processor
IOW/IOR
INT
IER
0 00 0
IIR
THR
RHR
Figure 20. Interrupt Mode Operation
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