TL16C752D Datasheet, PDF (30/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
Table 7. TL16C752D Internal Registers^{() ()} (continued)
ADDRESS REGISTER
110
MSR
Xoff1 ⁽⁶⁾
TCR ⁽⁷⁾
111
SPR
Xoff2 ⁽⁶⁾
TLR ⁽⁷⁾
R/W
(3)
R
RW
RW
RW
RW
RW
ACCESS
CONSIDERATION
LCR[7:0] ≠
10111111
LCR[7:0] =
10111111
EFR[4] = 1 &
MCR[6] = 1
LCR[7:0] ≠
10111111
LCR[7:0] =
10111111
EFR[4] = 1 &
MCR[6] = 1
FIFORdy⁽⁸⁾ R
MCR[4] = 0 &
MCR[2] = 1
BIT 7
CD#
1
bit 7
1
bit 7
0
bit 7
1
bit 7
1
bit 7
0
RX FIFO D
status
0
BIT 6
RI#
1
bit 6
1
bit 6
0
bit 6
1
bit 6
1
bit 6
0
RX FIFO C
status
0
BIT 5
DSR#
1
bit 5
1
bit 5
0
bit 5
1
bit 5
1
bit 5
0
RX FIFO B
status
0
BIT 4
CTS#
0
bit 4
1
bit 4
0
bit 4
1
bit 4
1
bit 4
0
RX FIFO A
status
0
BIT 3
∆CD#
0
bit 3
1
bit 3
0
bit 3
1
bit 3
1
bit 3
0
TX FIFO D
status
0
(7) This register is only accessible when EFR[4] = 1 and MCR[6] = 1
(8) This register is accessible when any CS A-B = 0, MCR[2] = 1, and loopback MCR[4] = 0 is disabled
BIT 2
∆RI#
0
bit 2
1
bit 2
0
bit 2
1
bit 2
1
bit 2
0
TX FIFO C
status
0
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BIT 1
∆DSR#
0
bit 1
1
bit 1
0
bit 1
1
bit 1
1
bit 1
0
TX FIFO B
status
0
BIT 0
∆CTS#
0
bit 0
1
bit 0
0
bit 0
1
bit 0
1
bit 0
0
TX FIFO A status
0
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