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TL16C752D Datasheet, PDF (33/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO
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TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
8.5.6 Line Status Register (LSR)
Table 10 shows line status register bit settings.
Table 10. LSR Bit Settings
BIT
BIT SETTINGS
0
0 = No data in the receive FIFO
1 = At least one character in the RX FIFO
1
0 = No overrun error
1 = Overrun error has occurred.
2
0 = No parity error in data being read from RX FIFO
1 = Parity error in data being read from RX FIFO
3
0 = No framing error in data being read from RX FIFO
1 = Framing error occurred in data being read from RX FIFO (that is, received data did not have a valid stop bit)
4
0 = No break condition
1 = A break condition occurred and associated byte is 00 (that is, RX was low for at least one character time frame)
0 = Transmit hold register is not empty
5
1 = Transmit hold register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is
enabled.
6
0 = Transmitter hold and shift registers are not empty.
1 = Transmitter hold and shift registers are empty.
0 = Normal operation
7
1 = At least one parity error, framing error or break indication are stored in the receiver FIFO. Bit 7 is cleared when no
errors are present in the FIFO.
When the LSR is read, LSR[4:2] reflects the error bits [BI, FE, PE] of the character at the top of the RX FIFO
(next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the RX FIFO is
output directly onto the output data-bus, DI[4:2], when the LSR is read. Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO.
NOTE
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
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