TL16C752D Datasheet, PDF (23/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

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TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
8.3.1.10 Polled Mode Operation
In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 21 shows polled
mode operation.
Processor
IOW/IOR
LSR
IER
0 00 0
THR
RHR
Figure 21. FIFO Polled Mode Operation
8.3.1.11 Break and Timeout Conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4 ×
programmed word length) + 12 bits and there is at least one byte stored in the RX FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
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