TL16C752D Datasheet, PDF (12/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
TX (A–B)
INT (A–B)
IOW
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
Next
Data
Start
Bit
t_22d
t_23d
Active
Active
Tx Ready
t_24d
Active
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TX (A–B)
IOW
D0–D7
TXRDY (A–B)
TXRDY
16-Baud Rate Clock
Figure 7. Transmit Timing
Start
Bit
Data Bits (5–8)
Stop
Bit
D0
D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Active
Next
Data
Start
Bit
Byte 1
t _28d
T27d
Active
Transmitter Ready
Figure 8. Transmit Ready Timing in Non-FIFO Mode
Transmitter
Not Ready
12
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