TL16C752D Datasheet, PDF (24/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
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8.3.1.12 Programmable Baud Rate Generator
The TL16C752D UART contains a programmable baud generator that divides reference clock by a divisor in the
range between 1 and (2¹⁶ − 1). The output frequency of the baud rate generator is 16× the baud rate. An
additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in the following. The
formula for the divisor is:
Divisor = (XTAL crystal input frequency / prescaler) / (desired baud rate X 16)
Where
prescaler =
1 when CLKSEL = high during reset, or MCR[7] is set to 0 after reset
4 when CLKSEL = high during reset, or MCR[7] is set to 1 after reset
Figure 22 shows the internal prescaler and baud rate generator circuitry.
XTAL1
XTAL2
Internal
Oscillator
Logic
Prescaler Logic
(Divide By 1)
Input Clock
Prescaler Logic
(Divide By 4)
MCR[7] = 0
Reference
Clock
Band Rate
Generator
Logic
MCR[7] = 1
Internal
Band Bate Clock
For Transmitter
and Receiver
Figure 22. Prescaler and Baud Rate Generator Block Diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and
most significant byte of the baud rate divisor. If DLL and DLH are both 0, the UART is effectively disabled,
because no baud clock is generated. The programmable baud rate generator is provided to select both the
transmit and receive clock rates. Table 5 and Table 6 show the baud rate and divisor correlation for the crystal
with frequency 1.8432 and 3.072 MHz, respectively.
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