TL16C752D Datasheet, PDF (36/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
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8.5.10 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register, which provides the source of the interrupt in a prioritized manner. Table 14
shows interrupt identification register bit settings.
Table 14. IIR Bit Settings
BIT
BIT SETTINGS
0
0 = An interrupt is pending
1 = No interrupt is pending
3:1
3-Bit encoded interrupt. See Table 13
4
1 = Xoff or special character has been detected
5
CTS/RTS low to high change of state
7:6
Mirror the contents of FCR[0]
The interrupt priority list is illustrated in Table 15.
PRIORITY
LEVEL
1
2
2
3
4
5
6
BIT 5
0
0
0
0
0
0
1
BIT 4
0
0
0
0
0
1
0
BIT 3
0
1
0
0
1
0
0
Table 15. Interrupt Priority List
BIT 2
1
1
1
0
0
0
0
BIT 1
1
0
0
1
0
0
0
BIT 0 INTERRUPT SOURCE
0
Receiver line status error
0
Receiver timeout interrupt
0
RHR interrupt
0
THR interrupt
0
Modem interrupt
0
Received Xoff signal or special character
0
CTS, RTS change of state from active (low) to inactive (high)
8.5.11 Enhanced Feature Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 16 shows the enhanced feature
register bit settings.
Table 16. EFR Bit Settings
BIT
BIT SETTINGS
3:0
Combinations of software flow control can be selected by programming bit 3 to bit 0. See Table 1.
Enhanced functions enable bit.
4
0 = Disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]
1 = Enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a
write enable
0 = Normal operation
5
1 = Special character detect. Received data is compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to 1 to indicate a special character has been detected.
RTS flow control enable bit
6
0 = Normal operation
1 = RTS flow control is enabled, that is, RTS pin goes high when the receiver FIFO HALT trigger level TCR[3:0] is
reached, and goes low when the receiver FIFO RESTORE transmission trigger level TCR[7:4] is reached.
CTS flow control enable bit
7
0 = Normal operation
1 = CTS flow control is enabled, that is, transmission is halted when a high signal is detected on the CTS pin
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