TL16C752D Datasheet, PDF (16/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
Functional Block Diagrams (continued)
Bus
Interface
Control
and
Status Block
Modem Control Signals
Control Signals
Status Signals
Divisor
Control Signals
Status Signals
Baud-Rate
Generator
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UART_CLK
64-Byte
Receiver FIFO
Receiver Block
Logic
Vote
Logic
Int_Rx
RX
IrDA
RX
64-Byte
Transmitter FIFO
Transmitter Block
Logic
Int_Tx
IrDA
TX
TX
NOTE: The vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a
majority vote to determine the logic level received. The vote logic operates on all bits received.
Figure 15. TL16C752D Functional Block Diagram – Control Blocks
8.3 Feature Description
8.3.1 Functional Description
The TL16C752D UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive
software overhead by buffering received and transmitted characters. Both the receiver and transmitter FIFOs can
store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have
selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signaling of DMA
transfers.
The TL16C752D UART has selectable hardware flow control and software flow control. Both schemes
significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon and Xoff characters.
The TL16C752D device includes a programmable baud rate generator that can divide the timing reference clock
by a divisor between 1 and 65535. A bit (MCR7) can be used to invoke a prescaler (divide by 4) off the reference
clock, prior to the baud rate generator input. The divide by 4 prescaler is selected when MCR7 is set to 1.
8.3.1.1 Trigger Levels
The TL16C752D UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in
effect, the trigger level is the default value of one byte. The selectable trigger levels are available through the
FCR. The programmable trigger levels are available through the TLR.
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