TL16C752D Datasheet, PDF (11/56 Pages) Texas Instruments – TL16C752D Dual UART With 64-Byte FIFO

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RX (A–B)
INT (A–B)
IOR
TL16C752D
SLLSEN8B – SEPTEMBER 2015 – REVISED MARCH 2016
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
Next
Data
Start
Bit
t_20d
Active
t_21d
Active
RX (A–B)
RXRDY (A–B)
RXRDY
IOR
RX (A–B)
RXRDY (A–B)
RXRDY
IOR
16-Baud Rate Clock
Figure 4. Receive Timing
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Next
Data
Start
Bit
t_25d
Active
Data
Ready
t_26d
Active
Figure 5. Receive Ready Timing in Non-FIFO Mode
Start
Bit
Data Bits (5–8)
Stop
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
First Byte
That Reaches
The Trigger
Level
t_25d
Active
Data
Ready
t_26d
Active
Figure 6. Receive Timing in FIFO Mode
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