SLDS145B Datasheet, PDF (8/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
timing diagrams
t_r
t_f
DVI
Outputs
80% V_OD
20% V_OD
Figure 1. Rise and Fall Time for DVI Outputs
IDCK−
t_h(IDF)
IDCK+
t_su(IDF)
t_su(IDR)
t_h(IDR)
DATA[23:0], DE,
V_IH
HSYNC, VSYNC
V_IL
Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK±
IDCK+
t_su(ID)
t_h(ID)
t_su(ID)
t_h(ID)
DATA[23:0], DE,
V_IH
HSYNC, VSYNC
V_IL
Figure 3. Dual Edge Data Setup/Hold Times to IDCK+
TX+
50%
TX−
t_sk(D)
Figure 4. Analog Output Intra-Pair ± Differential Skew
TXN 50%
t_sk(CC)
TXM 50%
Figure 5. Analog Output Channel-to-Channel Skew
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