SLDS145B Datasheet, PDF (5/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
Terminal Functions (Continued)
TERMINAL
NAME
NO.
DKEN
35
V_REF
3
I/O
DESCRIPTION
I
Data de-skew enable. The de-skew function can be enabled either through I²C or by this pin when I²C
is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in
discrete trim increments. The amount of trim per increment is defined by t_(STEP).
When I²C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by
pins DK[3:1] (see the data de-skew section). A low level disables de-skew and the default trim setting is
used.
When I²C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I²C.
In this configuration, the DKEN pin should be tied to either GND or V_DD to avoid a floating input.
I
Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,
VSYNC, and IDCK±).
For high-swing 3.3-V input signal levels, V_REF should be tied to V_DD.
For low-swing input signal levels, V_REF should be set to half of the maximum input voltage level. See
the recommended operating conditions section for the allowable range for V_REF.
The desired V_REF voltage level is typically derived using a simple voltage-divider circuit.
PD
10
I
Power down (active low). In the powerdown state, only the digital I/O buffers and I²C interface remain
active.
When I²C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects
the powerdown mode.
When I²C is enabled (ISEL = high), the power-down state is selected through I²C. In this configuration,
the PD pin should be tied to GND.
Note: The default register value for PD is low, so the device is in powerdown mode when I²C is first
enabled or after an I²C RESET.
Reserved
RESERVED
34
In This pin is reserved and must be tied to GND for normal operation.
DVI Differential Signal Output Pins
TX0+
TX0−
25
O Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video and
24
HSYNC and VSYNC during the blanking interval.
TX1+
TX1−
28
O Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and
27
CTL[1] during the blanking interval.
TX2+
TX2−
31
O Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and
30
CTL[3:2] during the blanking interval.
TXC+
TXC−
22
O DVI differential output clock.
21
TFADJ
19
Power and Ground Pins
I
Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the
value of the pullup resistor R_TFADJ connected to TV_DD.
DV_DD
PV_DD
TV_DD
DGND
1, 12, 33
18
23, 29
16, 48, 64
Power Digital power supply. Must be set to 3.3 V nominal.
Power PLL power supply. Must be set to 3.3 V nominal.
Power Transmitter differential output driver power supply. Must be set to 3.3 V nominal.
Ground Digital ground
PGND
17
Ground PLL ground
TGND
20, 26, 32 Ground Transmitter differential output driver ground
NC
49
NC No connection required. If connected, tie high.
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