SLDS145B Datasheet, PDF (20/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
register descriptions (continued)
CFG
Sub-Address = 0B
Read Only
7
6
5
4
3
2
1
0
CFG[7:0] (D[23:16])
This read-only register contains the state of the inputs D[23:16]. These pins can be used to provide the user with
selectable configuration data through the I²C bus.
RESERVED
7
Sub-Address = 0E−0C
Read/Write
6
5
4
3
2
RESERVED
RESERVED
RESERVED
Default = 0x97D0A9
1
0
These read/write registers have no effect on TFP410 operation.
DE_DLY
7
Sub-Address = 32
Read/Write
6
5
4
3
2
DE_DLY[7:0]
Default = 0x00
1
0
This read/write register defines the number of pixels after HSYNC goes active that DE is generated, when the DE
generator is enabled.
DE_CTL
7
Reserved
6
DE_GEN
Sub-Address = 33
5
4
VS_POL
HS_POL
Read/Write
3
2
Reserved
DE_DLY[8]: This read/write register contains the top bit of DE_DLY.
HS_POL: This read/write register sets the HSYNC polarity.
0: HSYNC is considered active low.
1: HSYNC is considered active high.
Pixel counts are reset on the HSYNC active edge.
VS_POL: This read/write register sets the VSYNC polarity.
0: VSYNC is considered active low.
1: VSYNC is considered active high.
Line counts are reset on the VSYNC active edge.
DE_GEN: This read/write register enables the internal DE generator.
0: DE generator is disabled. Signal required on DE pin
1: DE generator is enabled. DE pin is ignored.
Default = 0x00
1
0
DE_DLY[8]
DE_TOP
7
Sub-Address = 34
Read/Write
6
5
4
3
2
DE_TOP[7:0]
Default = 0x00
1
0
This read/write register defines the number of pixels after VSYNC goes active that DE is generated, when the DE
generator is enabled.
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