SLDS145B Datasheet, PDF (7/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc specifications
PARAMETERS
TEST CONDITIONS
V_IH
High-level input voltage (CMOS input)
V_REF = DV_DD
0.5 V  V_REF  0.95 V
V_IL
Low-level input voltage (CMOS input)
V_REF = DV_DD
0.5 V  V_REF  0.95 V
V_OH
High-level digital output voltage (open-drain output) V_DD = 3 V, I_OH = 20 μA
V_OL
Low-level digital output voltage (open-drain output) V_DD = 3.6 V, I_OL = 4 mA
I_IH
High-level input current
V_I = 3.6 V
I_IL
Low-level input current
V_I = 0
V_H
V_L
V_SWING
V_OFF
DVI single-ended high-level output voltage
DVI single-ended low-level output voltage
DVI single-ended output swing voltage
DVI single-ended standby/off output voltage
AV_DD = 3.3 V ± 5%,
R_T† = 50 Ω ± 10%,
R_TFADJ = 510 Ω ± 1%
I_PD
Power-down current (see Note 3)
I_IDD
Normal power supply current
Worst case pattern^‡
† _{RT is the single-ended termination resistance at the receiver end of the DVI link.}
‡ _{Black and white checkerboard pattern, each checker is one pixel wide.}
NOTE 3: Assumes all inputs to the transmitter are not toggling.
MIN
0.7 V_DD
V_REF + 0.2
2.4
AV_DD − 0.01
AV_DD − 0.6
400
AV_DD − 0.01
TYP
MAX UNIT
V
0.3V_DD
V
V_REF − 0.2
V
0.4 V
±25 μA
±25 μA
AV_DD + 0.01 V
AV_DD − 0.4
V
600 mV_P-P
AV_DD + 0.01 V
200
500 μA
200
250 mA
ac specifications
f_(IDCK)
t_(pixel)
t_(IDCK)
t_(ijit)
t_r
t_f
t_sk(D)
t_sk(CC)
t_ojit
t_su(IDF)
t_h(IDF)
PARAMETER
IDCK frequency
Pixel time period (see Note 4)
IDCK duty cycle
IDCK clock jitter tolerance
DVI output rise time (20-80%) (see Note5)
DVI output fall time (20-80%) (see Note 5)
DVI output intra-pair + to − differential skew (see Note 6)
DVI output inter-pair or channel-to-channel skew (see Note 6)
DVI output clock jitter, max. (see Note 7)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge
TEST CONDITIONS
f_(IDCK) = 165 MHz
Single edge
(BSEL=1, DSEL=0,
DKEN=0, EDGE=0)
MIN
25
6.06
30%
75
75
1.2
1.3
TYP MAX UNIT
165 MHz
40 ns
70%
2
ns
240 ps
240 ps
50
ps
1.2 ns
150 ps
ns
ns
t_su(IDR)
Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge
Single edge
1.2
ns
(BSEL=1, DSEL=0,
t_h(IDR)
Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge
DKEN=0, EDGE=1)
1.3
ns
t_su(ID)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising
edge
Dual edge
(BSEL=0, DSEL=1,
DKEN=0)
0.9
ns
t_h(ID)
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising
edge
Dual edge (BSEL=0,
DSEL=1, DKEN=0)
1
ns
t_(STEP)
De-skew trim increment
DKEN = 1
350
ps
NOTES: 4. t_(pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t_(pixel).
5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.
6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.
7. Relative to input clock (IDCK).
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