SLDS145B Datasheet, PDF (3/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

functional block diagram
IDCK±
DATA[23:0]
DE
VSYNC
HSYNC
V_REF
EDGE/HTPLG
DKEN
MSEN
PD
ISEL/RST
CTL/A/DK[3:1]
BSEL/SCL
DSEL/SDA
Universal Input
12/24 Bit
I/F
Data
Format
I²C Slave I/F
For DDC
TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
T.M.D.S. Transmitter
Encoder
Encoder
Encoder
Serializer
Serializer
Serializer
Control
1.8-V Regulators
With Bypass
PLL
Capacitors
TX2±
TX1±
TX0±
TXC±
TFADJ
TERMINAL
NAME
NO.
Input
DATA[23:12]
36−47
DATA[11:0]
50−55,
58−63
IDCK−
56
IDCK+
57
DE
2
HSYNC
4
VSYNC
5
Terminal Functions
I/O
DESCRIPTION
I
The upper 12 bits of the 24-bit pixel bus
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode,
the state of DATA[23:16] is input to the I²C register CFG. This allows 8 bits of user configuration data to
be read by the graphics controller through the I²C interface (see the I²C register descriptions section).
Note: All unused data inputs should be tied to GND or V_DD.
I
The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge
(both rising and falling) of the clock.
I
Differential clock input. The TFP410 supports both single-ended and fully differential clock input
modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the
single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock
input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK− signals as the timing
reference for latching incoming data DATA[23:0], DE, HSYNC, & VSYNC. The differential clock input
mode is only available in the low signal swing mode.
I
Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel
data or control data on any given input clock cycle. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes
HSYNC, VSYNC and CTL[3:1].
I
Horizontal sync input
I
Vertical sync input
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