SLDS145B Datasheet, PDF (18/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
register descriptions (continued)
RESERVED
7
Sub-Address = 07−05
6
5
Read Only
4
3
2
RESERVED[7:0]
RESERVED[7:0]
RESERVED[15:8]
Default = 0x641400
1
0
CTL_1_MODE
7
RSVD
6
TDIS
Sub-Address = 08
5
4
VEN
HEN
Read/Write
3
2
DSEL
BSEL
Default = 0xFE
1
0
EDGE
PD
PD: This read/write register contains the power-down mode.
0: Power down (default after RESET)
1: Normal operation
EDGE: This read/write register contains the edge select mode.
0: Input data latches to the falling edge of IDCK+
1: Input data latches to the rising edge of IDCK+
BSEL: This read/write register contains the input bus select mode.
0: 12-bit operation with dual-edge clock
1: 24-bit operation with single-edge clock
DSEL:This read/write register is used in combination with BSEL and V_REF to select the single-ended or differential
input clock mode. In the high-swing mode, DSEL is a don’t care since IDCK is always single-ended.
HEN: This read/write register contains the horizontal sync enable mode.
0: HSYNC input is transmitted as a fixed low
1: HSYNC input is transmitted in its original state
VEN: This read/write register contains the vertical sync enable mode.
0: VSYNC input is transmitted as a fixed low
1: VSYNC input is transmitted in its original state
TDIS: This read/write register contains the T.M.D.S. disable mode.
0: T.M.D.S. circuitry enable state is determined by PD.
1: T.M.D.S. circuitry is disabled.
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