SLDS145B Datasheet, PDF (22/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
I²C interface (continued)
The basic access read cycle consists of the following:
1. A start condition
2. A slave write address cycle
3. A sub-address cycle
4. A restart condition
5. A slave read address cycle
6. Any number of data cycles
7. A stop condition
The start and stop conditions are shown in Figure 10. The high to low transition of SDA while SCL is high defines
the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,
data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving
device. Thus, each data/address cycle contains 9 bits as shown in Figure 11.
SCL
123456789123456789123456789
SDA
Slave Address
Sub-Address
Data
Figure 11. I²C Access Cycles
Stop
Following a start condition, each I²C device decodes the slave address. The TFP410 responds with an
acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.
During subsequent sub-address and data cycles, the TFP410 responds with acknowledge as shown in
Figure 12. The sub-address is auto-incremented after each data cycle.
The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device
may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal
high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 13.
The slave address consists of 7 bits of address along with 1 bit of read/write information (read = 1, write = 0)
as shown below in Figures 11 and 12. For the TFP410, the selectable slave addresses (including the R/W bit)
using A[3:1]are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles and 0x71, 0x73, 0x75,
0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.
Where:
S Slave Address W A Sub-Address A Data A Data A P
From Master
From Slave
A Acknowledge
S Start condition
P Stop Condition
Figure 12. I²C Write Cycle
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