SLDS145B Datasheet, PDF (19/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
register descriptions (continued)
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
CTL_2_MODE
7
6
VLOW
Sub-Address = 09
5
4
MSEL[3:1]
Read/Write
3
2
TSEL
RSEN
Default = 0x00
1
0
HTPLG
MDI
MDI: This read/write register contains the monitor detect interrupt mode.
0: Detected logic level change in detection signal (to clear, write one to this bit)
1: Logic level remains the same
HTPLG: This read only register contains the hot plug detection input logic state.
0: Logic level detected on the EDGE/HTPLG pin (pin 9)
1: High level detected on the EDGE/HTPLG pin (pin 9)
RSEN: This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems.
0: A powered-on receiver is not detected
1: A powered-on receiver is detected (i.e. connected to the DVI transmitter outputs)
TSEL: This read/write register contains the interrupt generation source select.
0: Interrupt bit (MDI) is generated by monitoring RSEN
1: Interrupt bit (MDI) is generated by monitoring HTPLG
MSEL: This read/write register contains the source select of the monitor sense output pin.
000: Disabled. MSEN output high
001: Outputs the MDI bit (interrupt)
010: Outputs the RSEN bit (receiver detect)
011: Outputs the HTPLG bit (hot plug detect)
VLOW: This read only register indicates the V_REF input level.
0: This bit is a logic level (0) if the V_REF analog input selects high-swing inputs
1: This bit is a logic level (1) if the V_REF analog input selects low-swing inputs
CTL_3_MODE
7
6
DK[3:1]
Sub-Address = 0A
5
4
DKEN
Read/Write
3
2
CTL[3:1]
Default = 0x80
1
0
RSVD
CTL[3:1]:This read/write register contains the values of the three CTL[3:1] bits that are output on the DVI port during
the blanking interval.
DKEN: This read/write register controls the data de-skew enable.
0: Data de-skew is disabled, the values in DK[3:1] are not used
1: Data de-skew is enabled, the de-skew setting is controlled through DK[3:1]
DK[3:1]: This read/write register contains the de-skew setting, each increment adjusts the skew by t_(STEP).
000: Step 1 (minimum setup/maximum hold)
001: Step 2
010: Step 3
011: Step 4
100: Step 5 (default)
101: Step 6
110: Step 7
111: Step 8 (maximum setup/minimum hold)
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