SLDS145B Datasheet, PDF (11/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
universal graphics controller interface modes
Table 1 is a tabular representation of the different modes for the universal graphics controller interface. The
12-bit mode is selected when BSEL=0 and the 24-bit mode when BSEL=1. The 12-bit mode uses dual-edge
clocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge
in 24-bit mode, or the primary latching edge in 12-bit mode. When EDGE=1, the data input is latched on the rising
edge of the input clock; and when EDGE=0, the data input is latched on the falling edge of the input clock. A
fully differential input clock is available only in the low-swing mode. Single-ended clocking is not recommended
in the low-swing mode as this decreases common-mode noise rejection.
Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I²C is enabled (ISEL=1)
and by input pins when I²C is disabled (ISEL=0).
Table 1. Universal Graphics Controller Interface Options (Tabular Representation)
V_REF
BSEL
0.55 V − 0.9 V
0
EDGE
0
DSEL
0
BUS WIDTH LATCH MODE CLOCK EDGE
CLOCK MODE
12-bit
Dual-edge
Falling
Differential (see Note 9 and 10)
0.55 V − 0.9 V
0
0
1
12-bit
Dual-edge
Falling
Single-ended
0.55 V – 0.9 V
0
1
0
12-bit
Dual-edge
Rising
Differential (see Note 9 and 10)
0.55 V − 0.9 V
0
1
1
12-bit
Dual-edge
Rising
Single-ended
0.55 V – 0.9 V
1
0
0
24-bit
Single-edge
Falling
Single-ended
0.55 V – 0.9 V
1
0
1
24-bit
Single-edge
Falling
Differential (see Note 9 and 11)
0.55 V – 0.9 V
1
1
0
24-bit
Single-edge
Rising
Single-ended
0.55 V – 0.9 V
1
1
1
24-bit
Single-edge
Rising
Differential (see Note 9 and 11)
DV_DD
0
0
X
12-bit
Dual-edge
Falling
Single-ended (see Note 12)
DV_DD
0
1
X
12-bit
Dual-edge
Rising
Single-ended (see Note 12)
DV_DD
1
0
X
24-bit
Single-edge
Falling
Single-ended (see Note 12)
DV_DD
1
1
X
24-bit
Single-edge
Rising
Single-ended (see Note 12)
NOTES: 9. The differential clock input mode is only available in the low signal swing mode (i.e., V_REF p 0.9 V).
10. The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.
11. The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.
12. In the high-swing mode (V_REF = DV_DD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11