SLDS145B Datasheet, PDF (21/29 Pages) Texas Instruments – TFP410 TI PanelBus DIGITAL TRANSMITTER

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
register descriptions (continued)
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
DE_CNT
7
Sub-Address = 37−36
Read/Write
6
5
4
3
2
DE_CNT[7:0]
Reserved
Default = 0x0000
1
0
DE_CNT[10:8]
These read/write registers define the width of the active display, in pixels, when the DE generator is enabled.
DE_LIN
7
Sub-Address = 39−38
Read/Write
6
5
4
3
2
DE_LIN[7:0]
Reserved
Default = 0x0000
1
0
DE_LIN[10:8]
These read/write registers define the height of the active display, in lines, when the DE generator is enabled.
H_RES
7
Sub-Address = 3B−3A
Read Only
6
5
4
3
2
1
0
H_RES[7:0]
Reserved
H_RES[10:8]
These read-only registers return the number of pixels between consecutive HSYNC pulses.
V_RES
7
Sub-Address = 3D−3C
Read Only
6
5
4
3
2
1
0
V_RES[7:0]
Reserved
V_RES[10:8]
These read-only registers return the number of lines between consecutive VSYNC pulses.
I²C interface
The I²C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCL
clock line and the SDA serial data line. The basic I²C access cycles are shown in Figure 10 and Figure 11.
SDA
SCL
Start Condition (S)
Stop Condition (P)
Figure 10. I²C Start and Stop Conditions
The basic access write cycle consists of the following:
1. A start condition
2. A slave address cycle
3. A sub-address cycle
4. Any number of data cycles
5. A stop condition
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