CC430F5125 Datasheet, PDF (8/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
CC430F512x Functional Block Diagram
XIN XOUT
(32kHz)
P1.x/P2.x
2x8
P3.x
1x8
P5.x
1x2
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RF_XIN RF_XOUT
(26MHz)
DMA
Controller
3 Channel
CPUXV2
incl. 16
Registers
EEM
(S: 3+1)
JTAG
Interface
Spy-Bi-
Wire
MCLK
Unified
Clock
System
ACLK
SMCLK
Comp_B
REF
Voltage
Reference
I/O Ports
P1/P2
2x8 I/Os
PA
1x16 I/Os
I/O Ports
P3
1x8 I/Os
I/O Ports
P5
1x2 I/Os
Bus
Cntrl
Logic
MAB
MAB
MDB
MDB
Flash
32kB
16kB
8kB
MDB
MAB
RAM
4kB
2kB
incl.
Backup
RAM
(128B)
CRC16
SYS
Watch-
dog
Port
Mapping
Controller
MPY32
Power
Mgmt
LDO
SVM/SVS
Brownout
RTC_D
(Calendar
+
Counter
Mode)
LPM3.5
Domain
TA0
5 CC
Registers
TA1
3 CC
Registers
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
AES128
Security
En-/De-
cryption
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
Sub-1GHz
Radio
(CC1101)
CPU Interface
MODEM
Frequency
Synthesizer
RF/ANALOG
TX & RX
NOTE: Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for ports P1 and P2.
RF_P RF_N
8
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