CC430F5125 Datasheet, PDF (57/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)⁽¹⁾Figure 19Figure 20
PARAMETER
TEST CONDITIONS
PMM
COREVx
V_CC
MIN
t_STE,LEAD STE lead time, STE low to clock
1.8 V
11
0
3.0 V
8
2.4 V
7
3
3.0 V
6
t_STE,LAG STE lag time, Last clock to STE high
1.8 V
3
0
3.0 V
3
2.4 V
3
3
3.0 V
3
t_STE,ACC
STE access time, STE low to SOMI
data out
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_STE,DIS
STE disable time, STE high to SOMI
high impedance
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_SU,SI
SIMO input data setup time
1.8 V
5
0
3.0 V
5
2.4 V
2
3
3.0 V
2
t_HD,SI
SIMO input data hold time
1.8 V
5
0
3.0 V
5
2.4 V
5
3
3.0 V
5
0
t_VALID,SO SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
3
1.8 V
3.0 V
2.4 V
3.0 V
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
1.8 V
18
0
3.0 V
12
2.4 V
10
3
3.0 V
8
TYP MAX UNIT
ns
ns
66
50
ns
36
30
30
23
ns
16
13
ns
ns
76
60
ns
44
40
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(USCI), t_{SU,MI(Master)} + t_{VALID,SO(USCI)}).
For the master's parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 17 and Figure 18.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 17
and Figure 18.
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