CC430F5125 Datasheet, PDF (63/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
10-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
E_I
Integral linearity error
1.4 V ≤ (VEREF+ - VEREF-)min ≤ 1.6 V
1.6 V < (VEREF+ - VEREF-)min ≤ V_AVCC
E_D
Differential linearity error
(VEREF+ - VEREF-)min ≤ (VEREF+ - VEREF-),
C_VEREF+ = 20 pF
(VEREF+ - VEREF-)min ≤ (VEREF+ - VEREF-),
E_O
Offset error
Internal impedance of source R_S < 100 Ω,
C_VEREF+ = 20 pF
Gain error, external reference
(VEREF+ - VEREF-)min ≤ (VEREF+ - VEREF-),
E_G
Gain error, external reference,
buffered
C_VEREF+ = 20 pF
Gain error, internal reference
See ⁽¹⁾
V_CC
MIN TYP
-1.0
-1.0
-1.0
-1.0
-1.0
-5
-1.5
Total unadjusted error, external
reference
(VEREF+ - VEREF-)min ≤ (VEREF+ - VEREF-),
E_T
Total unadjusted error, external
reference, buffered
C_VEREF+ = 20 pF
-2.0 ±1.0
-5 ±1.0
Total unadjusted error, internal
reference
See ⁽¹⁾
-1.5 ±1.0
(1) Dominated by the absolute voltage of the integrated reference voltage.
MAX
+1.0
+1.0
UNIT
LSB
+1.0 LSB
+1.0 LSB
+1.0 LSB
+5 LSB
+1.5 %V_REF
+2.0 LSB
+5 LSB
+1.5 %V_REF
REF, External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
VEREF+
PARAMETER
Positive external
reference voltage input
TEST CONDITIONS
VEREF+ > VEREF-⁽²⁾
V_CC
MIN TYP
1.4
VEREF-
Negative external
reference voltage input
VEREF+ > VEREF-⁽³⁾
0
VEREF+ -
VEREF-
Differential external
reference voltage input
VEREF+ > VEREF-⁽⁴⁾
1.4
I_(VEREF+)
I_(VEREF-)
Static input current
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V
f_ADC10CLK = 5 MHz, ADC10SHTx = 0x0001,
Conversion rate 200 ksps
2.2 V, 3 V
±8.5
I_(VEREF+)
I_(VEREF-)
Static input current
1.4 V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 V
f_ADC10CLK = 5 MHZ, ADC10SHTX = 0x1000,
Conversion rate 20 ksps
2.2 V, 3 V
C_(VEREF+/-)
Capacitance at VEREF+
or VEREF- terminal
See ⁽⁵⁾
10
MAX UNIT
AV_CC V
1.2 V
AV_CC V
±26 µA
±1 µA
µF
(1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
(5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VEREF to decouple the dynamic current required for an external
reference source if it is used for the ADC10_A. See also the CC430 Family User's Guide (SLAU259).
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