CC430F5125 Datasheet, PDF (42/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
www.ti.com
Low-Power Mode Supply Currents (Into V_CC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)^{(1) (2)}
PARAMETER
Temperature (T_A)
V_CC PMMCOREVx
-40°C
25°C
60°C
85°C
TYP MAX TYP MAX TYP MAX TYP MAX
2.2 V
0
I_LPM0,1MHz
Low-power mode 0⁽³⁾⁽⁴⁾
3.0 V
3
80
100
90
110
80
100
90
110
80
100
90
110
80
100
90
110
I_LPM2
2.2 V
0
Low-power mode 2⁽⁵⁾⁽⁴⁾
3.0 V
3
6.5
11
6.5
11
6.5
11
6.5
11
7.5
12
7.5
12
7.5
12
7.5
12
0
1.8
2.0
2.6
3.0
4.0
4.4
5.9
I_LPM3,XT1LF
Low-power mode 3,
crystal mode⁽⁶⁾⁽⁴⁾
3.0 V
1
2
1.9
2.0
2.1
2.2
3.2
3.4
4.8
5.1
3
2.0
2.2
2.9
3.5
4.8
5.3
7.4
0
0.9
Low-power mode 3,
1
1.0
I_LPM3,VLO,WDT
VLO mode, only WDT
enabled ^{(7) (4)}
3.0 V
2
1.1
3
1.1
1.1
2.3
2.1
3.7
3.5
5.6
1.2
2.3
3.9
1.3
2.5
4.2
1.3
2.6
2.6
4.5
4.4
7.1
0
0.8
1.0
2.2
2.0
3.6
3.4
5.5
1
0.9
1.1
2.2
3.8
I_LPM4
Low-power mode 4⁽⁸⁾⁽⁴⁾
3.0 V
2
1.0
1.2
2.4
4.1
3
1.0
1.2
2.5
2.5
4.4
4.3
7.0
2.2 V
n/a
0.7
I_LPM3.5
Low-power mode 3.5⁽⁹⁾
3.0 V
n/a
1.0
0.9
1.4
1.0
1.5
1.2
1.7
1.0
1.5
1.2
1.7
1.4
1.8
2.2 V
n/a
0.2
I_LPM4.5
Low-power mode 4.5⁽¹⁰⁾
3.0 V
n/a
0.3
0.25
0.7
0.4
0.9
0.6
1.1
0.3
0.8
0.4
0.9
0.7
1.2
UNIT
µA
µA
µA
µA
µA
µA
µA
µA
µA
(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load
capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = f_DCO = 1 MHz
(4) Current for brownout and high-side supervisor (SVS_H) normal mode included. Low-side supervisor (SVS_L) and low-side monitor (SVM_L)
disabled. High-side monitor disabled (SVM_H). RAM retention enabled.
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); f_ACLK = 32768 Hz, f_MCLK = 0 MHz, f_SMCLK = f_DCO = 0 MHz; DCO setting = 1
MHz operation, DCO bias generator enabled.
(6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK = 32768 Hz, f_MCLK = f_SMCLK = f_DCO = 0 MHz
(7) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); f_ACLK = f_VLO, f_MCLK = f_SMCLK = f_DCO = 0 MHz
(8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); f_DCO = f_ACLK = f_MCLK = f_SMCLK = 0 MHz
(9) Internal regulator disabled. No data retention except Backup RAM. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF =
1 (LPMx.5), RTC active (Calendar mode) with RTCHOLD = 0 (LPM3.5) and f_XT1 = 32768 Hz, f_DCO = f_ACLK = f_MCLK = f_SMCLK = 0 MHz.
(10) Internal regulator disabled. No data retention except bBackup RAM. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF
= 1 (LPMx.5), RTC disabled with RTCHOLD = 1 (LPM4.5), f_DCO = f_ACLK = f_MCLK = f_SMCLK = 0 MHz.
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