CC430F5125 Datasheet, PDF (10/118 Pages) Texas Instruments – MSP430 SoC With RF Core

CC430F614x
CC430F514x
CC430F512x
ECCN 5E002 TSPA - Technology / Software Publicly Available
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
www.ti.com
TERMINAL
NAME
P1.7/ PM_UCA0CLK/
PM_UCB0STE/ R03
P1.6/ PM_UCA0TXD/
PM_UCA0SIMO/ R13/ LCDREF
P1.5/ PM_UCA0RXD/
PM_UCA0SOMI/ R23
LCDCAP/ R33
COM0
P5.7/ COM1/ S26
P5.6/ COM2/ S25
P5.5/ COM3/ S24
P5.4/ S23
VCORE
DVCC
P1.4/ PM_UCB0CLK/
PM_UCA0STE/ S22
P1.3/ PM_UCB0SIMO/
PM_UCB0SDA/ S21
P1.2/ PM_UCB0SOMI/
PM_UCB0SCL/ S20
P1.1/ PM_RFGDO2/ S19
P1.0/ PM_RFGDO0/ S18
P3.7/ PM_SMCLK/ S17
P3.6/ PM_RFGDO1/ S16
P3.5/ PM_TA0CCR4A/ S15
P3.4/ PM_TA0CCR3A/ S14
P3.3/ PM_TA0CCR2A/ S13
Table 3. CC430F614x Terminal Functions
I/O ⁽¹⁾
NO.
DESCRIPTION
General-purpose digital I/O with port interrupt and mappable secondary function
1 I/O Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
2
I/O
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
General-purpose digital I/O with port interrupt and mappable secondary function
3 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
4 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
5 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
6 I/O LCD common output COM1 for LCD backplane
LCD segment output S26
General-purpose digital I/O
7 I/O LCD common output COM2 for LCD backplane
LCD segment output S25
General-purpose digital I/O
8 I/O LCD common output COM3 for LCD backplane
LCD segment output S24
9
I/O
General-purpose digital I/O
LCD segment output S23
10
Regulated core power supply
11
Digital power supply
General-purpose digital I/O with port interrupt and mappable secondary function
12 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
LCD segment output S22
General-purpose digital I/O with port interrupt and mappable secondary function
13 I/O Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data
LCD segment output S21
General-purpose digital I/O with port interrupt and mappable secondary function
14 I/O Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock
LCD segment output S20
General-purpose digital I/O with port interrupt and mappable secondary function
15 I/O Default mapping: Radio GDO2 output
LCD segment output S19
General-purpose digital I/O with port interrupt and mappable secondary function
16 I/O Default mapping: Radio GDO0 output
LCD segment output S18
General-purpose digital I/O with mappable secondary function
17 I/O Default mapping: SMCLK output
LCD segment output S17
General-purpose digital I/O with mappable secondary function
18 I/O Default mapping: Radio GDO1 output
LCD segment output S16
General-purpose digital I/O with mappable secondary function
19 I/O Default mapping: TA0 CCR4 compare output or capture input
LCD segment output S15
General-purpose digital I/O with mappable secondary function
20 I/O Default mapping: TA0 CCR3 compare output or capture input
LCD segment output S14
General-purpose digital I/O with mappable secondary function
21 I/O Default mapping: TA0 CCR2 compare output or capture input
LCD segment output S13
(1) I = input, O = output
10
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