CC430F5125 Datasheet, PDF (55/118 Pages) Texas Instruments – MSP430 SoC With RF Core

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ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F614x
CC430F514x
CC430F512x
SLAS555A – NOVEMBER 2012 – REVISED FEBRUARY 2013
USCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
1 MHz
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
t_τ
UART receive deglitch time⁽¹⁾
TEST CONDITIONS
V_CC
2.2 V
3V
MIN TYP
50
50
MAX
600
600
UNIT
ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
V_CC
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
MIN TYP MAX UNIT
f_SYSTEM MHz
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)⁽¹⁾Figure 17Figure 18
PARAMETER
TEST CONDITIONS
PMM
COREVx
V_CC
MIN TYP
t_SU,MI
SOMI input data setup time
1.8 V
55
0
3.0 V
38
2.4 V
30
3
3.0 V
25
t_HD,MI
SOMI input data hold time
1.8 V
0
0
3.0 V
0
2.4 V
0
3
3.0 V
0
t_VALID,MO
SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
1.8 V
0
3.0 V
2.4 V
3
3.0 V
t_HD,MO
SIMO output data hold time⁽³⁾ C_L = 20 pF
1.8 V
-10
0
3.0 V
-8
2.4 V
-10
3
3.0 V
-8
MAX UNIT
ns
ns
ns
ns
20
ns
18
16
ns
15
ns
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 17 and Figure 18.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 17 and Figure 18.
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