CC3200MOD_15 Datasheet, PDF (47/66 Pages) Texas Instruments – CC3200MOD SimpleLink™ Wi-Fi® and Internet-of-Things Module Solution, a Single-Chip Wireless MCU

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CC3200MOD
SWRS166 – DECEMBER 2014
5.8.1.1 SRAM
The CC3200 family provides up to 256KB of zero-wait-state, on-chip SRAM. Internal RAM is capable of
selective retention during LPDS mode. This internal SRAM is located at offset 0x2000 0000 of the device
memory map.
Use the µDMA controller to transfer data to and from the SRAM.
When the device enters low-power mode, the application developer can choose to retain a section of
memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The
application developer can choose the amount of memory to retain in multiples of 64KB. For more
information, see the API guide.
5.8.1.2 ROM
The internal zero-wait-state ROM of the CC3200 device is at address 0x0000 0000 of the device memory
and programmed with the following components:
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
The bootloader is used as an initial program loader (when the serial flash memory is empty). The CC3200
DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.
The DriverLib APIs in ROM can be called by applications to reduce flash memory requirements and free
the flash memory to be used for other purposes.
5.8.1.3 Memory Map
Table 5-5 describes the various MCU peripherals and how they are mapped to the processor memory. For
more information on peripherals, see the API document.
START ADDRESS
0x0000 0000
0x2000 0000
0x2200 0000
0x4000 0000
0x4000 4000
0x4000 5000
0x4000 6000
0x4000 7000
0x4000 C000
0x4000 D000
0x4002 0000
0x4002 0800
0x4003 0000
0x4003 1000
0x4003 2000
0x4003 3000
0x400F 7000
0x400F E000
0x400F F000
0x4200 0000
0x4401 C000
END ADDRESS
0x0007 FFFF
0x2003 FFFF
0x23FF FFFF
0x4000 0FFF
0x4000 4FFF
0x4000 5FFF
0x4000 6FFF
0x4000 7FFF
0x4000 CFFF
0x4000 DFFF
0x400 07FF
0x4002 0FFF
0x4003 0FFF
0x4003 1FFF
0x4003 2FFF
0x4003 3FFF
0x400F 7FFF
0x400F EFFF
0x400F FFFF
0x43FF FFFF
0x4401 EFFF
Table 5-5. Memory Map
DESCRIPTION
On-chip ROM (Bootloader + DriverLib)
Bit-banded on-chip SRAM
Bit-band alias of 0x2000 0000 through 0x200F FFFF
Watchdog timer A0
GPIO port A0
GPIO port A1
GPIO port A2
GPIO port A3
UART A0
UART A1
I²C A0 (Master)
I²C A0 (Slave)
General-purpose timer A0
General-purpose timer A1
General-purpose timer A2
General-purpose timer A3
Configuration registers
System control
µDMA
Bit band alias of 0x4000.0000 through 0x400F.FFFF
McASP
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