CC3200MOD_15 Datasheet, PDF (40/66 Pages) Texas Instruments – CC3200MOD SimpleLink™ Wi-Fi® and Internet-of-Things Module Solution, a Single-Chip Wireless MCU

CC3200MOD
SWRS166 – DECEMBER 2014
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Table 4-13. ADC Electrical Specifications (continued)
PARAMETER
DESCRIPTION
CONDITION AND
MIN
ASSUMPTIONS
Driving source
impedance
FCLK
Clock rate
Successive approximation input
clock rate
Input capacitance
Number of channels
F_sample
F_input_max
Sampling rate of each ADC
Maximum input signal frequency
SINAD
I_active
Signal-to-noise and distortion Input frequency dc to 300 Hz
55
and 1.4 V_pp sine wave input
Active supply current
Average for analog-to-digital
during conversion without
reference current
I_PD
Power-down supply current for
core supply
Total for analog-to-digital when
not active (this must be the SoC
level test)
Absolute offset error
FCLK = 10 MHz
Gain error
TYP
10
3.2
4
62.5
60
1.5
1
±2
±2%
Figure 4-16 shows the ADC clock timing diagram.
MAX
100
31
Internal Ch
Repeats Every 16 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
2 µs
UNIT
Ω
MHz
pF
KSPS
kHz
dB
mA
µA
mV
ADC CLOCK
= 10 MHz
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 0
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Sampling
4 cycles
SAR Conversion
16 cycles
EXT CHANNEL 1
Sampling
4 cycles
SAR Conversion
16 cycles
INTERNAL CHANNEL
Figure 4-16. ADC Clock Timing
4.11.2.7 Camera Parallel Port
The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in
a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.
Figure 4-17 shows the timing diagram for the camera parallel port.
Figure 4-17. Camera Parallel Port Timing Diagram
Table 4-14 lists the timing parameters for the camera parallel port.
40
Specifications
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