CC3200MOD_15 Datasheet, PDF (39/66 Pages) Texas Instruments – CC3200MOD SimpleLink™ Wi-Fi® and Internet-of-Things Module Solution, a Single-Chip Wireless MCU

www.ti.com
CC3200MOD
SWRS166 – DECEMBER 2014
4.11.2.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.
Figure 4-15 shows the JTAG timing diagram.
J2
J3
J4
TCK
TMS
J7
J8
TMS Input Valid
J7
J8
TMS Input Valid
TDI
J11
J9
J10
TDI Input Valid
J9
J10
TDI Input Valid
J1
TDO
TDO Output Valid
TDO Output Valid
Figure 4-15. JTAG Timing
SWAS031-069
Table 4-12 lists the JTAG timing parameters.
PARAMETER
NUMBER
J1
J2
J3
J4
J7
J8
J9
J10
J11
Table 4-12. JTAG Timing Parameters
PARAMETER PARAMETER NAME
MIN
fTCK
Clock frequency
tTCK
Clock period
tCL
Clock low period
tCH
Clock high period
tTMS_SU
TMS setup time
1
tTMS_HO
TMS hold time
16
tTDI_SU
TDI setup time
1
tTDI_HO
TDI hold time
16
tTDO_HO
TDO hold time
MAX
15
1/fTCK
tTCK/2
tTCK/2
15
UNIT
MHz
ns
ns
ns
4.11.2.6 ADC
Table 4-13 lists the ADC electrical specifications.
Table 4-13. ADC Electrical Specifications
PARAMETER
Nbits
INL
DESCRIPTION
Number of bits
Integral nonlinearity
DNL
Input range
Differential nonlinearity
CONDITION AND
ASSUMPTIONS
MIN
TYP
12
Worst-case deviation from
–2.5
histogram method over full scale
(not including first and last three
LSB levels)
Worst-case deviation of any step –1
from ideal
0
MAX
2.5
4
1.4
UNIT
Bits
LSB
LSB
V
Copyright © 2014, Texas Instruments Incorporated
Submit Documentation Feedback
Specifications
39