CC3200MOD_15 Datasheet, PDF (35/66 Pages) Texas Instruments – CC3200MOD SimpleLink™ Wi-Fi® and Internet-of-Things Module Solution, a Single-Chip Wireless MCU

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CC3200MOD
SWRS166 – DECEMBER 2014
4.11.2.1.2 SPI Slave
Figure 4-10 shows the timing diagram for the SPI slave.
I3
I2
I4
CLK
I6
I7
MISO
I9
I8
MOSI
Figure 4-10. SPI Slave Timing Diagram
SWAS032-017
Table 4-5 lists the timing parameters for the SPI slave.
Table 4-5. SPI Slave Timing Parameters
PARAMETER
NUMBER
I1
PARAMETER ⁽¹⁾
F
I2
Tclk
I3
tLP
I4
tHT
I5
D
I6
tIS
I7
tIH
I8
tOD
I9
tOH
PARAMETER NAME
Clock frequency @ VBAT = 3.3 V
Clock frequency @ VBAT ≤ 2.1 V
Clock period
Clock low period
Clock high period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
MIN
50
45%
4
4
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
MAX
20
12
25
25
55%
20
24
UNIT
MHz
ns
ns
ns
ns
ns
ns
4.11.2.2 McASP
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of
transmit and receive sections that operate synchronously and have programmable clock and frame-sync
polarity. A fractional divider is available for bit-clock generation.
4.11.2.2.1 I2S Transmit Mode
Figure 4-11 shows the timing diagram for the I2S transmit mode.
I2
I1
I3
McACLKX
McAFSX
I4
I4
McAXR0/1
SWAS032-015
Figure 4-11. I2S Transmit Mode Timing Diagram
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