GC1115 Datasheet, PDF (46/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
www.ti.com
TIMER_SYNC
0x1C (28)
Type: Read/Write Value at RESET: 0x0000
The TIMER_SYNC register selects the synchronization source for the GC1115’s software timer. In addition, Bit
15 of TIMER_SYNC determines whether the software timer runs once (Bit 15 = 0) or runs repeatedly (Bit 15 = 1).
BITS
[2:0]
[14:3]
15
STAGE_SYNC selection:
0: NEVER
3: SYNC_A
6: invalid
Reserved
Timer repeat:
DESCRIPTION
1: SW_TRIGGER
4: SYNC_B
7: invalid
2: TIMER
5: ALWAYS
0: do not repeat (run
once)
1: repeat
DELAY_SYNC 0x1D (29)
Type: Read/Write Value at RESET: 0x0000
The DELAY_SYNC register selects the synchronization source that triggers the GC1115’s CANCEL_DELAY
being copied to PDC stages selected by DELAY_MASK. Under normal circumstances, all cancel RAMs contain
the same set of cancellation coefficients. When this is the case, DELAY_MASK is set to 0xF, and
CANCEL_DELAY1 thru CANCEL_DELAY4 are copied to their respective internal registers as soon as
DELAY_SYNC is triggered. Under normal circumstances, DELAY_SYNC can be set to ALWAYS, i.e. as soon as
CANCEL_DELAY1 thru CANCEL_DELAY4 are written, their corresponding internal registers are immediately
updated.
BITS
[2:0]
[15:3]
DESCRIPTION
DELAY_SYNC selection:
0: NEVER
1: SW_TRIGGER
2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
CANCEL_SYNC 0x1E (30)
Type: Read/Write Value at RESET: 0x0000
The CANCEL_SYNC register selects the synchronization source that causes the GC1115’s cancel coefficient
shadow RAM values to be copied to the canceler RAMs whose corresponding RESOURCE_MASK bit is set. At
GC1115 initialization, all cancel RAMs are normally initialized using the same set of cancellation coefficients.
When this occurs, RESOURCE_MASK is set to 0xFF and the shadow RAM coefficients are copied to all
canceler RAMs as soon as the CANCEL_SYNC trigger occurs. It is convenient for the microprocessor or DSP to
use SW_TRIGGER as the CANCEL_SYNC source. As soon as the shadow RAM has been initialized, the
microprocessor or DSP can then simply write a 0x20 to SW_TRIGGER, causing a trigger that only affects the
CANCEL_SYNC functional block.
BITS
[2:0]
[15:3]
DESCRIPTION
CANCEL_SYNC selection:
0: NEVER
1: SW_TRIGGER 2: TIMER
3: SYNC_A
4: SYNC_B
5: ALWAYS
6: invalid
7: invalid
Reserved
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