GC1115 Datasheet, PDF (44/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
Signal Generator and CRC Registers (Addresses 21– 24)
SIG_GEN_CTL 0x15 (21) Type: Read/Write Value at RESET: 0x0000
www.ti.com
The SIG_GEN_CTL register controls the operation of a signal generator. When enabled, the signal generator’s
outputs feed the I and Q inputs of PDC Stage 1. In pseudo-LFSR mode, the GC1115 generates a signal with a
PAR of approximately 10 dB. In order to properly generate a periodic signal and its related periodic CRC, the
GC1115 must be initialized by parameters provided by TI. If CRC generation is not required, the CRC_RESULT
register can simply be ignored, and the signal generator can be used without any restrictions.
Bit 7 of INT_MAP indicates when the CRC result is available. When Bit 7 of INT_MASK is set, the GC1115 will
interrupt the controlling microprocessor or DSP to indicate that the CRC_RESULT register can be read. Once
this bit is set, the microprocessor or DSP must manually clear Bit 7 of INT_MAP prior to subsequent “CRC result
available” interrupts.
BITS
[1:0]
[15:2]
DESCRIPTION
Signal generator and CRC control:
00 = Signal Generator and CRC Generator are DISABLED
01 = Signal Generator in DC or sawtooth mode (CRC enabled)
if SIG_GEN_INC = 0, generate DC value of SIG_GEN_BASE
if SIG_GEN_INC > 0, generate a sawtooth waveform
10 = pseudo-LFSR with 10 dB PAR (CRC generator enabled)
11 = External (CRC generator enabled)
Reserved
SIG_GEN_BASE 0x16 (22) Type: Read/Write Value at RESET: 0x0000
The SIG_GEN_BASE register specifies the output value for DC signal generation, or the starting accumulator
value for sawtooth signal generation. While SIG_GEN_BASE is a 16-bit value, the GC1115 DC/sawtooth signal
generator uses an 18-bit signed accumulator. SIG_GEN_BASE initializes the 16 LSBs of this 18-bit accumulator,
with proper sign extension. If bit 15 of SIG_GEN_BASE is set, bits 17, 16, and 15 of the internal 18-bit
accumulator will also be set. If bit 15 of SIG_GEN_BASE is clear, bits 17, 16, and 15 of the internal 18-bit
accumulator will also be clear. When the signal generator is enabled in DC or sawtooth mode, the 18-bit
accumulator value drives the 18-bit I input of PDC Stage 1. The bit-reversed version of the 18-bit accumulator
drives the 18-bit Q input of PDC Stage 2.
If GC1115 users want to observe the signal generator output at OUT__A and OUT__B, the detection and gain
thresholds for all enabled PDC stages should be set to 0xFFFF (i.e. no peaks will be found). Alternately, there
are two ways of achieving this: 1. All PDC stages are disabled in the CONTROL register, 2. No cancelers are
assigned to any PDC stages (using the four RESOURCE_CNT registers).
BITS
[15:0]
DESCRIPTION
Signal generator accumulator value (for DC and sawtooth signals)
[initial value of a signed, 18-bit internal accumulator]
SIG_GEN_INC 0x17 (23) Type: Read/Write Value at RESET: 0x0000
The SIG_GEN_INC register specifies the signed increment value for sawtooth signal generation. At each
IN_CLK, the signal generator adds the signed, 16-bit SIG_GEN_INC value to the current 18-bit accumulator.
BITS
[15:0]
DESCRIPTION
Signal generator increment value (for sawtooth signals)
[increment value applied to a signed, 18-bit internal accumulator]
44