GC1115 Datasheet, PDF (17/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144 – FEBRUARY 2005
DETAILED DESCRIPTION OF GC1115 FUNCTIONAL BLOCKS (continued)
The GC1115 microprocessor interface operates at speeds between 33 MHz and 100 MHz. Register read/write
accesses are faster than RAM read/write accesses. RAM access is used for snapshot RAM and shadow RAM.
Please refer to the timing diagrams for specific information on GC1115 register access rates. RAM access is
limited to 33 MHz.
TMS320Cxx
A[7:0]
D[15:0]
RD/WR
IOS
INT_A
GC1115
A[7:0]
D[15:0]
RD_
WR_
CS_
INT_
Figure 8. TMS320Cxx – GC1115 Interface
Users configure the GC1115 by writing control information into a set of 16-bit memory-mapped registers. The
registers are accessed using the GC1115’s A[7:0], D[15:0], CS, RD, and WR pins. The complete register map is
described in detail in a subsequent section. Certain GC1115 registers can be modified at any time during
GC1115 operation, while other registers may not be modified until certain conditions are met. Table 7 summarize
these restrictions. The GC1115 will strictly enforce the update restrictions listed in Table 7. If a particular update
condition is not met, the GC1115 will not update the specified register.
ADDRESS
0
1
2
3
4
5
6
7
8
9
10 (0xA)
11 (0xB)
12 (0xC)
13 (0xD)
14 (0xE)
15 (0xF)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
Table 7. GC1115 Register Updates
NAME
RESET
PLL_CONTROL
CLK_CONTROL
CONTROL
INT_MAP
INT_MASK
MASK_REV
SW_TRIGGER
IO_CONTROL
IO_MODE
POWER_CTL
POWER
DECIMATE
TIMER_HI_RST
TIMER_LO_RST
CANCEL_MODE
CANCEL_LENGTH
CANCEL_ADDRESS
CANCEL_DATA
RESOURCE_MASK
DELAY_MASK
WHEN CAN REGISTER BE UPDATED?
Any time
Any time
Any time
Any time
After GC1115 sends an interrupt
Any time
READ ONLY
Any time
Any time
After GC1115 receives IN_CLK
Any time
READ ONLY
Any time (after change, output may be invalid for a few samples)
When timer is OFF
When timer is OFF
Any time
Any time
Any time
Any time
Any time
Any time
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