GC1115 Datasheet, PDF (35/80 Pages) Texas Instruments – Crest Factor Reduction Processor

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REGISTER MAP
Global Registers (Addresses 0 – 14)
RESET
0x0
Type: Read/Write Value at RESET: 0x0033
GC1115
SLWS144 – FEBRUARY 2005
The RESET register provides separate bits to reset the GC1115 registers, the datapath, and the two PLLs.
Writing a 1 at a given bit location resets the functions mapped to that bit. Multiple bits can be set during each
write to the RESET register. The RESET register is unclocked, i.e. IN_CLK does not have to be toggling to
change RESET.
BITS
0
1
[3:2]
4
5
[16:6]
Configuration Reset
Datapath Reset
Reserved
CORE_PLL Reset
TX_PLL Reset
Reserved
DESCRIPTION
0 = running
0 = running
0 = running
0 = running
1 = reset
1 = reset
1 = reset
1 = reset
PLL_CONTROL 0x1
Type: Read/Write Value at RESET: 0x0000
The PLL_CONTROL register provides separate bits to control the GC1115’s core and transmit PLLs. The
PLL_CONTROL register is unclocked, i.e. IN_CLK does not have to be toggling to change
PLL_CONTROL.
Figure 7 demonstrates how the various bits of the PLL_CONTROL and CLK_CONTROL registers interact to
determine various GC1115 clock frequencies.
BITS
[1:0]
[7:2]
[9:8]
[15:10]
Core PLL Control:
00: PLL_CLL = IN_CLK
10: Reserved
Reserved
Transmit PLL Control:
00: PLL_CLL = IN_CLK
10: Reserved
Reserved
DESCRIPTION
01: PLL_CLK = 2 × IN_CLK
11: PLL_CLK = 4 × IN_CLK
01: PLL_CLK = 2 × IN_CLK
11: PLL_CLK = 4 × IN_CLK
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