GC1115 Datasheet, PDF (12/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
www.ti.com
SYNC Registers
The GC1115 contains a group of SYNC registers that control the behavior of thirteen different sync-related
functions. A subsequent section discusses GC1115 synchronization alternatives. This section only describes the
registers that must be properly initialized prior to GC1115 operation. Four datapath SYNC registers (RCV_SYNC,
STAGE_SYNC, DECIM_SYNC, and INTERP_SYNC) must be synchronized by a hardware event before the
GC1115 will process input samples. Four additional ancillary SYNC registers (DELAY_SYNC, CANCEL_SYNC,
RESOURCE_SYNC, and OUTGAIN_SYNC) must be synchronized by a hardware or software event before the
GC1115 properly applies cancellation coefficients and gains. TI recommends that the four datapath SYNC
registers be synchronized using a SYNC_A or SYNC_B hardware event, and that the ancillary SYNC registers
be synchronized using a SW_TRIGGER software event. Note that the SYNC registers must be initialized
BEFORE the corresponding hardware or software event occurs. For example, CANCEL_SYNC must be
initialized before the cancellation coefficients are transferred from the GC1115’s shadow RAM to the internal
canceler RAMs.
TSQD (Threshold) and RESOURCE_CNT Registers
The behavior of each PDC stage is controlled by two threshold registers (DETECT_TSQDx and GAIN_TSQDx)
and one resource (RESOURCE_CNTx) register, where x represents a specific stage (from 1 to 4). These 16-bit
registers contain the scaled threshold-squared values for the stage’s detection threshold and target peak level.
The 16-bit RESOURCE_CNT registers contain the number of cancellation resources (from 0 to 8) assigned to
the stage. NOTE: if a RESOURCE_CNT register is set to N (0 ≤ N ≤ 8), that PDC stage can cancel up to 4 × N
peaks simultaneously. A resource represents a canceler RAM. Up to four cancellation pulse generators are
supported by each canceler RAM.
INTERP Registers
A programmable output interpolator follows the GC1115’s four PDC stages. The GC1115 interpolator operates in
one of four modes:
• Bypass (the default condition)
• Interpolate by 2 (complex output)
• Interpolate by 2 (real output centered at fs/4)
• Interpolate by 4 (real output centered at fs/4)
The interpolator’s filter coefficients are programmable and must therefore be initialized, even in bypass mode,
before the GC1115 starts processing input samples. A total of 40 interpolator registers (from D0_COEF0 thru
D3_COEF9) must be initialized before the GC1115 processes input data.
OUT_GAIN and OUT_OFFSET Registers
The GC1115 output circuitry includes individual I and Q gain and offset registers that allow users to compensate
for I/Q imbalances in subsequent D/A converters and/or subsequent analog I/Q modulators. Because the
OUT_GAIN and OUT_OFFSET registers are user-programmable, they must be properly initialized before the
GC1115 starts processing input samples. OUT_GAIN registers are normally initialized to 0x2000 (gain of 1.0),
and OUT_OFFSET registers are usually initialized to 0x0000.
CANCEL_MODE, CANCEL_LENGTH, CANCEL_DELAY, Cancellation Coefficients
The GC1115 applies user-specified cancellation coefficients to detected peaks. Cancellation coefficients can
contain either real or complex values, to support both symmetric and asymmetric input spectra. For this reason,
the CANCEL_MODE, CANCEL_LENGTH, and CANCEL_DELAY registers must be properly initialized before the
GC1115 begins processing input samples. The cancellation coefficients themselves (in either real or complex
format) must be copied to the GC1115 canceler RAMs in a two-step process:
• The microprocessor or FPGA writes the cancellation coefficients to memory-mapped shadow RAM registers
• The shadow RAM registers are copied to one or more (of a total of eight) cancellation pulse SRAMs after a
CANCEL_SYNC event occurs.
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