GC1115 Datasheet, PDF (43/80 Pages) Texas Instruments – Crest Factor Reduction Processor

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GC1115
SLWS144 – FEBRUARY 2005
RESOURCE_MASK 0x13 (19)
Type: Read/Write Value at RESET: 0x00FF
The RESOURCE_MASK register contains an 8-bit field that determines which canceler RAMs will be initialized
after a CANCEL_SYNC trigger. By setting RESOURCE_MASK one bit at a time, canceler RAMs can be updated
one at a time. If all canceler RAMs were updated at the same time, there would be some short time period (a few
microseconds) in which no cancelers would be active. During this time, over-threshold peaks would pass through
the GC1115 without being canceled, which may be undesirable. Changing canceler RAMs one PDC stage at a
time allows subsets of canceler RAMs to be modified without disabling all cancelers.
BITS
0
1
2
3
4
5
6
7
[15:8]
Canceler RAM 0 update
status:
Canceler RAM 1 update
status:
Canceler RAM 2 update
status:
Canceler RAM 3 update
status:
Canceler RAM 4 update
status:
Canceler RAM 5 update
status:
Canceler RAM 6 update
status:
Canceler RAM 7 update
status:
Reserved
DESCRIPTION
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
NOTE:
The GC1115 user must ensure that the values in RESOURCE_CNT1, RE-
SOURCE_CNT2, RESOURCE_CNT3, and RESOURCE_CNT4 sum to 8 or less,
since there are only 8 canceler RAMs.
DELAY_MASK 0x12 (20) Type: Read/Write Value at RESET: 0x00FF
The DELAY_MASK register determines which peak detect and cancel (PDC) stages are updated when the
CANCEL_DELAY value is changed (i.e. when a DELAY_SYNC event occurs). Each of the four PDC stages has
its own CANCEL_DELAY value, so that different cancellation pulse delays could in theory be used by each PDC
stage. Under normal circumstances, however, CANCEL_DELAY will be identical for all PDC stages, since the
same cancellation pulse is normally stored in all canceler RAMs.
BITS
0
1
2
3
[15:4]
PDC Stage 0 update
status:
PDC Stage 1 update
status:
PDC Stage 2 update
status:
PDC Stage 3 update
status:
Reserved
DESCRIPTION
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
0 = do not update 1 = update
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