GC1115 Datasheet, PDF (11/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144 – FEBRUARY 2005
Setting specific bits in the RESET register activates these resets. Asserting the RESET pin of the GC1115 also
causes hardware reset. Hardware reset results in the following GC1115 conditions:
• All input pins are put in their high-impedance state
• All output pins are put in their high-impedance state
• All internal registers are reset to their RESET states
• All state machines are placed in their initial (idle) states
• No config registers can be modified before clearing the config reset.
GC1115 Initialization Sequence
The GC1115 initialization sequence requires the following register groups to be properly initialized:
1. RESET, PLL_CONTROL, CLK_CONTROL, IO_CONTROL
2. CONTROL, IO_MODE, DECIMATE, RESOURCE_MASK, DELAY_MASK
3. SYNC registers
4. TSQD detection threshold and target peak level registers
5. INTERP registers
6. OUT_GAIN, OUT_OFFSET
7. CANCEL_MODE, CANCEL_LENGTH, CANCEL_DELAY, cancellation coefficients
The following paragraphs describe in general terms how each of these registers is initialized to achieve the
desired user-specified peak reduction performance.
RESET, PLL_CONTROL, CLK_CONTROL, IO_CONTROL
The RESET register contains four bits that can individually reset:
• The memory-mapped registers
• The GC1115 internal datapath
• The “core” PLL
• The output PLL
At GC1115 startup, hardware RESET always precedes all other register accesses and this asserts all internal
reset registers. Configuration control reset must also be cleared before performing subsequent configuration
steps.
After the RESET bits have been asserted, the PLL_CONTROL and CLK_CONTROL registers should be
initialized to the desired values. The GC1115 normally operates at four times the input sample rate, while the
output clock rate is determined by several additional factors (decimation, interpolation, and output format and
mode). The CLK_CONTROL register determines the PLL multiplying factors that control the GC1115 core clock
and output clock frequencies. Finally, the IO_CONTROL register determines the input and output format (twos
complement or unsigned), the output enabled state (tri-stated or enabled), and the output bit width (18, 16, 14, or
12 bits).
The GC1115 PLLs require a warm-up time of at least 1 µs from PLL_CONTROL modification to PLL reset
release, and at least 100 µs from PLL_CONTROL and CLK_CONTROL modification to PLL reset release before
the internal clock is stable.
CONTROL, IO_MODE, DECIMATE, RESOURCE_MASK, DELAY_MASK
The CONTROL register contains six control bits that selectively enable or disable the four PDC stages, the
interpolator, and the soft limiter. The DECIMATE register allows users to decimate the input sample stream by 1
(no decimation) or 2. The RESOURCE_MASK register determines which of the eight cancellation pulse SRAMs
are updated with new cancel pulse coefficients when a CANCEL_SYNC event occurs. Similarly, the
DELAY_MASK register determines which of the four PDC stages are affected by changes to the CAN-
CEL_DELAY register when the DELAY_SYNC event occurs.
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