GC1115 Datasheet, PDF (37/80 Pages) Texas Instruments – Crest Factor Reduction Processor

www.ti.com
INT_MAP
0x4
Type: Read/Write Value at RESET: 0x0000
GC1115
SLWS144 – FEBRUARY 2005
The INT_MAP register indicates the reason(s) for a GC1115-initiated interrupt on the INT pin. Read INT_MAP to
determine whether that condition occurred (indicated by a “1”). Write a “1” to individual bits of INT_MAP to clear
(reset) specific interrupt conditions. INT_MAP operates in conjunction with INT_MASK (0x5) in generating an INT
signal.
The INT_MAP and INT_MASK registers work together to control interrupt sources that trigger the INT (interrupt)
output pin, which is normally tied to the hardware interrupt pin of the microprocessor or DSP chip that controls
the GC1115. Setting one or more bits of the INT_MASK register unmasks (enables) the corresponding interrupt
source in the INT_MAP register. The GC1115 contains eight possible interrupt sources. When the
microprocessor receives a signal on its INT pin, INT_MAP should be read to determine the specific cause (or
causes) of the interrupt.
BITS
0
1
2
3
4
5
6
7
[15:8]
DESCRIPTION
Snapshot RAM A capture/histogram completion
Snapshot RAM B capture/histogram completion
Snapshot RAM A histogram bin overflow
Snapshot RAM B histogram bin overflow
Timer counted down to zero
Input power measurement completed
Cancellation update has completed
CRC is available in the CRC_RESULT register
Reserved
INT_MASK
0x5
Type: Read/Write Value at RESET: 0x0000
The INT_MASK register determines whether the corresponding individual interrupt conditions in the INT_MAP
register will cause an INT interrupt. A “0” in a bit position disables the condition from causing an INT interrupt. A
“1” in a bit position allows the condition to cause an INT interrupt. The INT_MAP and INT_MASK registers work
together to control interrupt sources that trigger the INT (interrupt) output pin, which is normally tied to the
hardware interrupt pin of the microprocessor or DSP chip that controls the GC1115. Setting one or more bits of
the INT_MASK register unmasks (enables) the corresponding interrupt source in the INT_MAP register.
BITS
0
1
2
3
4
5
6
7
[15:8]
DESCRIPTION
Snapshot RAM A capture/histogram completed: disable (0) or enable (1) interrupt
Snapshot RAM B capture/histogram completed: disable (0) or enable (1) interrupt
Snapshot RAM A histogram bin overflow occurred: disable (0) or enable (1) interrupt
Snapshot RAM B histogram bin overflow occurred: disable (0) or enable (1) interrupt
Timer counted down to zero: disable (0) or enable (1)
Input power measurement
completed:
disable (0) or enable (1)
Cancellation update com-
pleted:
disable (0) or enable (1)
CRC available in
CRC_RESULT:
disable (0) or enable (1)
Reserved
37