GC1115 Datasheet, PDF (28/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
www.ti.com
Snapshot RAMs can be individually cleared (i.e. all entries set to zero) via control bits in the
SNAP_A_CONTROL and SNAP_B_CONTROL registers. Snapshot RAMs must be cleared prior to histogram
processing in order to zero all histogram counts.
Table 13 below shows how the snapshot RAM memory is used in capture and histogram modes. The addresses
in Table 13 are those that appear in the SNAP_A_ADDRESS or SNAP_B_ADDRESS registers.
Table 13. Snapshot RAM Addressing in Capture and Histogram Modes
MODE
Capture
Histogram
ADDRESS
0
1
2
3
...
2046
2047
0
1
2
3
...
2046
2047
CONTENTS
I[0] ⁽¹⁾
Q[0] ⁽¹⁾
I[1] ⁽¹⁾
Q[1] ⁽¹⁾
...
I[1023] ⁽¹⁾
Q[1023] ⁽¹⁾
HIST_MSW[0]
HIST_LSW[0]
HIST_MSW[1]
HIST_LSW[1]
...
HIST_MSW[1023]
HIST_LSW[1023]
(1) In capture mode, the 16 MSBs of the 18-bit samples are saved. MSW = most significant word (upper
16 bits), LSW = least significant word (lower 16 bits)
The SNAP_ADDRESS registers autoincrement with each SNAP_DATA access. This autoincrementing can result
in addresses that exceed the allowed snapshot RAM address range. The GC1115 resolves this address overflow
condition by resetting the SNAP_ADDRESS register to zero if an autoincrement generates an address value
greater than 2047.
Input Decimator
When the input signal is highly oversampled, the GC1115 user may want to decimate the complex input stream
prior to PDC processing. The DECIMATE register is provided for such circumstances. Under most conditions,
decimating an input signal will result in decreased performance because the higher, non-decimated sampling rate
better represents the signal. However, if the GC1115 is unable to accept the original input sampling rate,
decimation by 2 is provided as an option. GC1115 users wanting to use the 2x decimation settings must be
aware of decimation’s effects on GC1115 clock generation. Please refer to the Operating Modes section of this
document for details about how DECIMATE = 2 affects GC1115 operation.
Interpolation Operation
The GC1115 contains an interpolator stage after the fourth (final) PDC Stage. This interpolation stage can be
bypassed by clearing bit 4 of the CONTROL register. The interpolation stage also provides the following optional
capability:
• Interpolate by 2, real output, fs/4 modulation at the upsampled sampling rate
• Interpolate by 2, complex output
• Interpolate by 4, real output, fs/4 modulation at the upsampled sampling rate
The interpolate-by-4 stage uses 40 interpolation coefficients. These interp-by-4 coefficients are stored at
addresses 0x82 thru 0xA9. When the interpolate-by-4 stage is bypassed, the GC1115 requires the interp-by-4
coefficients shown in Table 14 (these are the default interp-by-4 values after a GC1115 RESET):
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