GC1115 Datasheet, PDF (15/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
www.ti.com
SLWS144 – FEBRUARY 2005
Clock Generation and PLL Operation
The GC1115 internal clock is normally generated through an on-board PLL. The PLL output frequency is 1, 2, or
4 times the frequency of the user-provided IN_CLK signal. For example, if the GC1115 is provided with an input
signal stream at 61.44 Msamp/sec and the PLL is configured to operate at 4x, the GC1115’s internal clock rate
will be 245.76 MHz. The GC1115’s functional blocks require four internal clock cycles per sample. This rule
affects the selection of related decimation and interpolation factors at a given input sampling rate. In addition, the
GC1115’s PLL divide-by-1 output frequency must fall between 100 MHz and 305 MHz. The 100 MHz minimum
PLL output clock rate is driven by the PLL design, while the 305 MHz maximum PLL output clock rate is limited
by the GC1115’s internal logic design. Alternately, the GC1115’s internal PLL can be bypassed, effectively using
IN_CLK directly as the GC1115 chip clock. However, in this mode, each input sample must be presented to the
input port(s) for four consecutive clock cycles, and the DECIM register must be set to 4. Using this bypass PLL
configuration allows users to operate the GC1115 at input sampling rates lower than 25 Msamp/sec.
NOTE:
Users may have to adjust the clock phase, relative to the data, for proper operation
during bypass PLL mode. Note that DECIM_SYNC may also have to be enabled on a
particular user-selected sample phase (1 of 4 phases) in order to achieve proper
operation during bypass PLL mode.
GC1115 users should be aware that the choice of input operating mode affects IN_CLK and thus also affects the
PLL clock. Specifically, GC1115 users must ensure the relationships shown in Table 5:
Table 5. IN_CLK, PLL Mode, and Core Clock
IN_CLK
(MHz)
25 - 75
50 - 130
100 - 130
1 - 125
PLL MODE
4x
2x
1x
Bypass
GC1115 CORE CLOCK
(MHz)
100 - 305
100 - 260
100 - 130
1 - 125
GC1115 users should also be aware that the core clock affects the choice of output operating mode. Specifically,
GC1115 users must ensure the relationships shown in Table 6. Notice that the odd-even output mode requires
that the interpolator operate in one of its two real-output modes: 2x real or 4x real.
GC1115 CORE CLOCK
(MHz)
100 - 305
100 - 260
100 - 260
100 - 130
100 - 305
100 - 260
Table 6. Core Clock and Interp Mode
INTERP MODE
OUTPUT FORMAT
Bypass
Bypass
2x (complex)
2x (complex)
2x (real)
4x (real)
Parallel
Muxed I/Q
Parallel
Muxed I/Q
Odd/Even
Odd/Even
OUTPUT CLOCK RATE
(MHz)
25 - 75
50 - 130
50 - 130
100 - 130
25 - 75
50 - 130
Summary of Registers Affecting GC1115 Clocks
The following GC1115 registers affect the input, core, and output clocks:
• PLL_CONTROL (0x1): determines PLL multiplier (1x, 2x, 4x, bypass) and source of Tx feedback
• CLK_CONTROL (0x2): determines relationship of IN_CLK and OUT_CLK to CORE_CLK
• IO_MODE (0x9): determines the number of channels (1 or 2), the input data format (parallel, muxed), and
the output data format (parallel, muxed, odd-even)
• DECIMATE (0xC): determines the downsampling of the input stream prior to GC1115 processing
• INTERP_CTL (0x80): determines the interpolator operating mode (bypass, 2x complex, 2x real, 4x real).
Note that INTERP_CTL and IO_MODE must be consistent to ensure proper operation!
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