GC1115 Datasheet, PDF (24/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
www.ti.com
eight canceler RAMs, the GC1115 can have up to 32 cancelers running independently per channel (four
cancelers per canceler RAM per channel). Cancellation pulse resources are allocated in groups of four per
channel, i.e. one canceler RAM at a time, to the four PDC stages. The registers RESOURCE_CNT1 thru
RESOURCE_CNT4 specify how many canceler RAMs are allocated to each PDC stage. The total number of
resources cannot exceed 8.
The CANCEL_ADDR and CANCEL_DATA registers are used to write to an independent “shadow RAM”. Using
the CANCEL_ADDR and CANCEL_DATA registers, the GC1115’s controlling microprocessor or DSP writes
cancellation coefficients and derivative values to this shadow RAM, and not directly to the canceler RAMs
themselves. When a COEF_SYNC synchronization event occurs, the contents of the shadow RAM are copied
(one value per internal GC1115 clock cycle) to those canceler RAMs whose corresponding bit is set in the
RESOURCE_MASK register. Using the RESOURCE_CNT registers, cancelers may be separately taken off-line,
updated, and brought back on-line in seamless operation. This approach ensures that the GC1115 is never
without cancellation resources.
To summarize, cancellation coefficients and their derivatives are written to canceler RAMs as follows:
1. Using CANCEL_ADDR and CANCEL_DATA, write up to 768 canceler coefficients and their derivatives to
shadow RAM
2. Using the RESOURCE_MASK register, specify which canceler RAMs are to be initialized from shadow RAM
when the COEF_SYNC event occurs
3. Using the COEF_SYNC register, specify which event (SW_TRIGGER, timer, SYNC_A, SYNC_B, etc.) will
trigger the COEF_SYNC event
4. After the COEF_SYNC event occurs, the GC1115 copies 3 × CANCEL_LENGTH values from shadow RAM
to the canceler RAMs selected by the RESOURCE_MASK register. During each internal clock cycle, one
shadow RAM value is copied simultaneously to the canceler RAMs enabled by their corresponding
RESOURCE_MASK bits. The total canceler RAM copy time depends on CANCEL_LENGTH and on the time
spent waiting for the selected RAMs to become idle, not on how many canceler RAMs are enabled for
update in the RESOURCE_MASK register.
5. After the GC1115 has copied 3 × CANCEL_LENGTH values from shadow RAM to canceler RAM, the
microprocessor or DSP can optionally be interrupted, if bit 6 of INT_MASK was set prior to Step 3.
Alternately, bit 6 of INT_MAP can be polled to determine when the shadow RAM copy completes.
Once the shadow RAM has been initialized, the process of copying the shadow RAM values to the canceler
RAMs occurs very quickly. For example, assuming an IN_CLK frequency of 61.44 MHz (16.3 ns), a
GC1115-internal clock rate of 4 × 61.44 MHz (4.1 ns), and a CANCEL_LENGTH of 87, the GC1115 only requires
3 × 87 × 4.1 ns = 1.07 µs to initialize all RESOURCE_MASK-enabled canceler RAMs, assuming all cancelers to
be updated were idle when the CANCEL_SYNC trigger occurred.
CANCEL_LENGTH and CANCEL_DELAY
In many GC1115 applications, a symmetric set of cancellation coefficients is chosen to match a symmetric carrier
configuration (i.e. the center frequencies of the carrier configuration are symmetric about DC). When cancellation
coefficients are symmetric, the delay introduced by a cancellation pulse with N coefficients is N/2, or half the
cancellation pulse length. The number of samples between the first coefficient and the largest coefficient
determines CANCEL_DELAY. Since the largest coefficient of symmetric filters is usually at the midpoint of the
filter, the delay is half the filter length.
Figure 9 illustrates a typical, symmetric FIR filter impulse response, whose largest coefficient is at tap 50, at the
midpoint of the 99-coefficient filter.
24