GC1115 Datasheet, PDF (2/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
VDD
(40)
VSS
(64)
FUNCTIONAL BLOCK DIAGRAM
VDDSHV
(31) VDDA1 VSSA1 VSS1 VDD1
VDDA2 VSSA2
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IN_CLK
IN_A[17:0]
IN_B[17:0]
SYNC_A_
SYNC_B_
JTAG[4:0]
TEST_MODE
VPP
CORE_CLK
PLL1
..
PLL2
32 Cancellation Pulse Generators
(allocate to PDC Stages in groups of 4)
PDC
Stage
1
PDC
Stage
2
PDC
Stage
3
PDC
Stage
4
Interp
2x, 4x
+ f_s/4
.
. Soft
. _Limiter
&
.. Output
Format
.
Test Signal Sync
Generator Control
Snapshot RAM
Input Selector
Interrupt
Generator
CRC
Gen.
Snapshot Snapshot
RAM A
RAM B
Microprocessor Registers
LOOP
(NC)
OUT_IQ_SEL
OUT_A[17:0]
OUT_B[17:0]
SYNC_OUT_
OUT_CLK
(NC)
A[7:0]
D[15:0]
CS_ RD_ WR_
INT_
RESET_
Related Documents
• GC1115 Evaluation Module (EVM) User’s Guide
• Application Note: GC1115 Configuration for UMTS (W-CDMA) Base Stations
• Application Note: GC1115 Configuration for 3GPP2 (cdma2000) Base Stations
• Matlab code for cancellation pulse design
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE
256-PBGA Plastic Ball Grid Array
DEVICE
GC1115IZDJ
2