GC1115 Datasheet, PDF (40/80 Pages) Texas Instruments – Crest Factor Reduction Processor

GC1115
SLWS144 – FEBRUARY 2005
POWER_CTL
0xA (10) Type: Read/Write Value at RESET: 0x0000
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The POWER_CTL register controls various power measurement parameters. Power measurement begins
automatically when bits [13:0] of POWER_CTL contain a non-zero value. The results of power measurement are
returned in the POWER register. The microprocessor controlling the GC1115 can request an interrupt at the
conclusion of power measurement by setting Bit 5 of INT_MASK (address 0x5).
BITS
[13:0]
14
15
DESCRIPTION
Number of POWER_CNT blocks⁽¹⁾ used to measure the average power (a value from 0 to
8191).
Measure in/out power
0 = input
1 = output
Measure Channel 0/Channel 1 0 = Channel 0 1 = Channel 1
power ⁽²⁾
(1) The number of samples per block is specified in the POWER_CNT register (address 0x7F). Normally
POWER_CNT is set to 0xFFFF (65,536 samples per block).
(2) During one-channel operation, setting POWER_CTL[15] to 1 will result in unpredictable power
measurements!
POWER
0xB (11) Type: Read Only Value at RESET: 0x0000
The POWER register contains the results of a power measurement process that was initiated according to the
parameters in the POWER_CTL register. The microprocessor controlling the GC1115 can request an interrupt at
the conclusion of power measurement by setting Bit 5 of INT_MASK (address 0x5).
BITS
[15:0]
DESCRIPTION
Average power measurement (0x0000 to 0xFFFF)
DECIMATE
0xC (12) Type: Read/Write Value at RESET: 0x0001
The DECIMATE register determines the decimation factor at the input of the GC1115. When set to 2, only every
second input sample is processed by the GC1115 datapath. A decimation factor of 2 is only required when input
clock rates below 25 MHz or above 75 MHz are used. When DECIMATE = 2, the GC1115 user must provide a
properly aligned synchronization signal (normally SYNC_A or SYNC_B) to select which input sample phase is
used to align the GC1115’s decimator. The DECIM_SYNC register selects the source of the decimator’s SYNC
signal.
BITS
[1:0]
[15:2]
Decimation factor:
01: no decimation
Reserved
DESCRIPTION
10: decimate by 2
TIMER_HI_RST 0xD (13) Type: Read/Write Value at RESET: 0x0000
The TIMER_HI_RST and TIMER_LO_RST registers (each 16 bits wide) determine the reset value of the
GC1115’s programmable software timer. This timer can be enabled to control the occurrence of SYNC events
during GC1115 processing. TIMER_HI_RST and TIMER_LO_RST are combined into a 32-bit unsigned value
that is clocked with every internal GC1115 clock. The TIMER_HI_RST and TIMER_LO_RST registers operate in
conjunction with the TIMER_SYNC register.
BITS
[15:0]
DESCRIPTION
Upper 16 bits of the GC1115’s 32-bit timer reset value.
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