RM0004 Datasheet, PDF (92/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

RM0004
Register model
Table 29. L1CSR0 field descriptions (continued)
Bits Name
Description
[Data]Cache lock bits flash clear. Clearing occurs regardless of the enable (L1CSR0[CE]) value.
CLFC ^{0 Default.}
55
DCLFC
1 Hardware initiates a cache lock bits flash clear operation. Cleared when the operation is
complete.
During a flash clear operation, writing a 1 causes undefined results; writing a 0 has no effect
[Data]Cache lock overflow allocate. Set by software to allow a lock request to replace a locked
line when a lock overflow situation exists. Implementation of this bit is optional.
CLOA
56
0 Indicates a lock overflow condition does not replace an existing locked line with the
DCLOA _{requested line}
1 Indicates a lock overflow condition replaces an existing locked line with the requested line
57–60 — Reserved, should be cleared.
[Data]Cache operation aborted.
CABT
61
0 No cache operation completed improperly
DCABT
1 Cache operation did not complete properly
[Data]Cache flash invalidate. Invalidation occurs regardless of the enable (L1CSR0[CE]) value.
CFI ^{0 No cache invalidate.}
62
DCFI
1 Cache flash invalidate operation. A cache invalidation operation is initiated by hardware.
Once complete, this bit is cleared.
During an invalidation operation, writing a 1 causes undefined results; writing a 0 has no effect.
[Data]Cache enable.
CE
63
0 The cache is not enabled. (not accessed or updated)
DCE
1 Enables cache operation.
2.11.2 L1 cache control and status register 1 (L1CSR1)
L1CSR1, defined as part of the EIS, is used for general control and status of the L1
instruction cache.
L1 cache control and status register 1 (L1CSR1)
011
SPR 1011
Access: supervisor read/write
Cache line locking APU fields
32
R
W
Reset
46 47 48 49 51 52 53 54 55 56 57 60 61 62 63
—
ICPE ICPI — ICSLC ICUL ICLO ICLFR ICLOA — ICABT ICFI ICE
All zeros
Table 30 describes the L1CSR1 fields.
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