RM0004 Datasheet, PDF (53/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Register model
RM0004
Table 7. Book E special purpose registers (by SPR abbreviation) (continued)
SPR
Abbreviation
Name
Defined SPR number
Decimal Binary
Access
Supervisor
only
TCR
TSR
Timer control register (TCR)
Timer status register (TSR)
340 01010 10100 Read/Write
Yes
336 01010 10000 Read/Clear
Yes
(2)
USPRG0 Software use sprs (SPRG0–
256 01000 00000 Read/Write
No
USPRG3 SPRG7 and USPRG0)⁽³⁾
259 01000 00011 Read-only
USPRG4
260 01000 00100 Read-only
USPRG5
261 01000 00101 Read-only
USPRG6
262 01000 00110 Read-only
USPRG7
263 01000 00111 Read-only
UTBL
Time base (TBU and TBL)
268 01000 01100 Read-only
No
UTBU Time base (TBU and TBL)
269 01000 01101 Read-only
No
XER
Integer exception register
(XER)
1
00000 00001 Read/Write
No
1. The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits
in the GPR can be cleared using mtspr.
2. The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in
the GPR can be cleared using mtspr.
3. User-mode read access to SPRG3 is implementation-dependent
Table 8 lists EIS-defined SPRs. Compilers should recognize the mnemonic name given in
this table when parsing instructions.
Table 8. EIS–defined SPRs (by SPR abbreviation)
SPR
abbreviation
Name
SPR
number
Access
Supervisor
only
Section/page
ATBL
ATBU
Alternate time base lower
Alternate time base upper
526 Read-only
No
527 Read-only
No
Section 2.15
on page 123
Section 2.15
on page 123
DBCR3
DSRR0
Debug control register 3
Debug save/restore register 0
561 Read/Write Yes
574
R/W
Yes
on page 115
on page 86
DSRR1 Debug save/restore register 1
575
R/W
Yes
on page 87
HID0
Hardware implementation dependent register
0
1008 Read/Write
Yes
Section 2.7.1
on page 71
HID1
Hardware implementation dependent register
1
1009 Read/Write
Yes
IVOR32
SPE/embedded floating-point APU
unavailable interrupt offset
528 Read/Write Yes
Section 2.7.2
on page 74
on page 83
IVOR33
Embedded floating-point data exception
interrupt offset
529 Read/Write Yes
on page 83
IVOR34
Embedded floating-point round exception
interrupt offset
530 Read/Write Yes
on page 83
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