RM0004 Datasheet, PDF (136/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

RM0004
Instruction model
Any attempt to execute a defined instruction results in one of the following events:
● An illegal instruction exception-type program interrupt, if an implementation does not
recognize the instruction
● An unimplemented instruction exception-type program interrupt, if the instruction is
recognized but not supported by the implementation and is not a floating-point
instruction
● An unimplemented instruction exception-type program interrupt, if the instruction is
recognized but not supported by the implementation, and is a floating-point instruction
and floating-point processing is enabled
● The floating-point unavailable interrupt if the instruction is recognized but is not
supported by the implementation or is a floating-point instruction and floating-point
processing is disabled
● The floating-point unavailable interrupt when floating-point processing is disabled and a
floating-point instruction is recognized and is not supported by the implementation
● If an instruction is recognized and supported by the implementation, the processor
performs the actions described in the rest of this document. The architected behavior
may cause other exceptions.
A defined instruction may be retained by future versions of Book E as a defined instruction,
or may be reclassified as a preserved instruction (process of removal from the architecture)
and eventually classified as reserved-illegal.
Allocated instruction class
This class of instructions contains the set of instructions (a set of primary opcodes, as well
as a set of extended opcodes for certain primary opcodes) used for implementation-specific
instructions. Table 62 lists blocks of opcodes allocated for implementation-dependent use.
.
Table 62. Allocated instructions
Primary opcode
Extended opcodes
0
All instruction encodings (bits 6–31) except 0x0000_0000⁽¹⁾.
All instruction encodings (bits 6–31)
4
SPE and embedded floating-point instructions
19
Extended opcodes (bits 21–30) 0buuuuu_0u11u
31
Extended opcodes (bits 21–30) uuuuu_0u11u
59
Extended opcodes (bits 21–30) uuuuu_0u10u
63
Extended opcodes (bits 21–30) uuuuu_0u10u (except 00000_01100 frsp)
1. Instruction encoding 0x0000_0000 is and always will be reserved-illegal.
Allocated instructions are allocated to purposes that are outside the scope of Book E for
implementation-dependent and application-specific use.
Any attempt to execute an allocated instruction results in one of the following:
● An illegal instruction exception-type program interrupt, if the instruction is not
recognized by the implementation
● An unimplemented instruction exception-type program interrupt, if the instruction is
recognized and enabled for execution but the implementation does not support direct
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