RM0004 Datasheet, PDF (127/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Register model
RM0004
2.16.3 Local control A registers (PMLCa0–PMLCa3)
The local control A registers 0–3 (PMLCa0–PMLCa3), function as event selectors and give
local control for the corresponding performance monitor counters. PMLCa works with the
corresponding PMLCb register.
Local control A registers (PMLCa0–PMLCa3)/
User local control A registers (UPMLCa0–UPMLCa3)
PMLCa0 (PMR144)
PMLCa1 (PMR145)
PMLCa2 (PMR146)
PMLCa3 (PMR147)
UPMLCa0 (PMR128)
UPMLCa1 (PMR129)
UPMLCa2 (PMR130)
UPMLCa3 (PMR131)
Access: PMLCa0–PMLCa3: supervisor-only
UPMLCa0–UPMLCa3: supervisor/user read-only
32 33 34 _{35 36} 37 38 40 41
47 48
63
R
FC FCS FCU FCM1 FCM0 CE —
EVENT
—
W
Reset
All zeros
Table 55. PMLCa0–PMLCa3 field descriptions
Bits
Name
Description
32
33
34
35
36
37
38–40
41–47
48–63
FC
FCS
FCU
FCM1
FCM0
CE
—
EVENT
—
Freeze counter
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented.
Freeze counter in supervisor state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 0.
Freeze counter in user state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 1.
Freeze counter while mark = 1
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 1.
Freeze counter while mark = 0
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 0.
Condition enable
0 PMCx overflow conditions cannot occur. (PMCx cannot cause interrupts,
cannot freeze counters.)
1 Overflow conditions occur when the most-significant-bit of PMCx is equal to
one.
It is recommended that CE be cleared when counter PMCx is selected for
chaining.
Reserved, should be cleared.
Event selector. Up to 128 events selectable.
Reserved, should be cleared.
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