RM0004 Datasheet, PDF (295/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Storage architecture
RM0004
The second bne- does not complete until CR0 has been set by the stwcx.. The stwcx. does
not set CR0 until it has completed (successfully or unsuccessfully). The lock is acquired
when the stwcx. completes successfully. Together, the second bne- and the subsequent
isync create an import barrier that prevents the load from data1 from being performed until
the branch is resolved to be not taken.
Obtain pointer and import shared memory
If lwarx and stwcx. are used to obtain a pointer into a shared data structure, an import
barrier is not needed if all the accesses to the shared data structure depend on the value
obtained for the pointer. The following example uses the fetch and add primitive (see
Section C.1.1: Synchronization primitives”) to obtain and increment the pointer.
In this example, it is assumed that the address of the pointer is in GPR 3, the value to be
added to the pointer is in GPR 4, and the old value of the pointer is returned in GPR 5.
loop:
value
lwarx
add
stwcx.
bne-
lwz
r5,0,r3
r0,r4,r5
# load pointer and reserve
# increment the pointer
r0,0,r3
# try to store new
loop
r7,data1(r5)
# loop if lost reservation
# load shared data
The load from data1 cannot be performed until the lwarx loads the pointer value into GPR 5.
The load from data1 may be performed out of order before the stwcx.. But if the stwcx.
fails, the branch is taken and the value returned by the load from data1 is discarded. If the
stwcx. succeeds, the value returned by the load from data1 is valid even if the load is
performed out of order, because the load uses the pointer value returned by the instance of
the lwarx that created the reservation used by the successful stwcx..
An isync could be placed between the bne- and the subsequent lwz, but no isync is
needed if all accesses to the shared data structure depend on the value returned by the
lwarx.
Atomic memory references
The Book E architecture defines the Load Word and Reserve Indexed (lwarx) and the store
word conditional indexed (stwcx.) instructions to provide an atomic update function for a
single, aligned word of memory. These instructions can be used to develop a rich set of
multiprocessor synchronization primitives. Note that atomic memory references constructed
using lwarx/stwcx. instructions depend on the presence of a coherent memory system for
correct operation. These instructions should not be expected to provide atomic access to
noncoherent memory.
The lwarx instruction performs a load word from memory operation and creates a
reservation for the same reservation granule that contains the accessed word. Reservation
granularity is implementation-dependent.
The lwarx instruction makes a nonspecific reservation with respect to the executing
processor and a specific reservation with respect to other masters. This means that any
subsequent stwcx. executed by the same processor, regardless of address, cancels the
reservation. Also, any bus write or invalidate operation from another processor to an
address that matches the reservation address cancels the reservation.
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