RM0004 Datasheet, PDF (309/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Storage architecture
Figure 19. Virtual address and TLB-entry comparison
TLB_entry[V]
TLB_entry[TS]
AS (from MSR[IS]
or MSR[DS])
Process ID
=?
=? ^{private page}
TLB_entry[TID]
=0? ^{shared page}
RM0004
TLB entry matches
virtual address
TLB_entry[EPN]
EA page number bits
=?
The generation of the physical address occurs as shown in Figure 20.
Figure 20. Effective-to-real address translation
MSR[DS] for data access
MSR[IS] for instruction fetch
32-Bit Effective Address
AS PID
32
Effective Page Number (EPN)
Virtual Address
Offset
n–1 n
63
TLB
multiple-entry
RPN field of matching entry
Real Page Number (RPN)
Offset
32
n–1 n
63
32-bit Real Address NOTE: n = 32–log₂(page size)
The EA combines with the AS and each PID register to form one virtual address for each
unique PID register value. Also. an implicit virtual address is formed using a PID value of 0.
Thus the following virtual addresses (VAs) are formed:
VA0 ← AS || 0 || EA
VA1 ← AS || PID0 || EA
...
VAn+1 ← AS || PIDn || EA
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