RM0004 Datasheet, PDF (313/1176 Pages) STMicroelectronics – Programmer’s reference manual for Book E processors

Storage architecture
RM0004
Where mask contains the same number of bits as a real address. The real address is then
used to access the memory subsystem using the TLB[ACM,VLE,W,I,M,G,E] fields from the
TLB entry to determine how the location should be accessed.
Page size and effective address bits compared
The page size defined for a TLB entry determines how many bits of the effective address
are compared with the corresponding EPN field in the TLB entry as shown in Table 185.
Table 185. Page size and EPN field comparison
SIZE Field Page Size (4^SIZEKbytes) EA to EPN Comparison (Bits 32–53; 2×SIZE)
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
1 Kbyte
4 Kbyte
16 Kbyte
64 Kbyte
256 Kbyte
1 Mbyte
4 Mbyte
16 Mbyte
64 Mbyte
256 Mbyte
1 Gbyte
EA[32–53] = ? EPN[32–53]
EA[32–51] = ? EPN[32–51]
EA[32–49] = ? EPN[0–49]
EA[32–47] = ? EPN[32–47]
EA[32–45] = ? EPN[32–45]
EA[32–43] = ? EPN[32–43]
EA[32–41] = ? EPN[32–41]
EA[32–39] = ? EPN[32–39]
EA[32–37] = ? EPN[32–37]
EA[32–35] = ? EPN[32–35]
EA[32–33] = ? EPN[32–33]
Permission attribute comparison
As part of the translation process, the selected TLB entry provides the access permission
bits (UX, SX, UW, SW, UR, SR), and memory/cache attributes (U0, U1, U2, U3, W, I, M, G,
and E) for the access. These bits specify whether or not the access is allowed and how the
access is to be performed.
If a matching TLB entry has been identified, Book E provides an access permission
mechanism that selectively grants shared access, grants execute access, grants read
access, grants write access, and prohibits access to areas of memory based on a number of
criteria. Book E defines the permission bits in TLB entries as follows:
● SR—Supervisor read permission
● SW—Supervisor write permission
● SX—Supervisor execute permission
● UR—User read permission
● UW—User write permission
● UX—User execute permission
If the virtual address translation comparison with TLB entries was successful, the
permission bits for the matching entry are checked as shown in Figure 21. If the access is
not allowed by the access permission mechanism, the processor generates an instruction or
data storage interrupt (ISI or DSI).
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